IP Library Granted Patent US 10,224,959
Granted Patent B2
US 10,224,959 · App. 15/935,117 · Granted Mar 5, 2019

Techniques for data compression verification

Inventors: Vinodh Gopal (Westborough, MA); James D. Guilford (Northborough, MA); Kirk S. Yap (Westborough, MA); Daniel F. Cutter (Maynard, MA); Wajdi K. Feghali (Boston, MA)
Assignee: INTEL CORPORATION
H03M7/6041H03M7/3086H03M7/6005H03M7/6011H04L1/24
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Quick Facts
Patent No.
US 10,224,959
App. No.
15/935,117
Granted
Mar 5, 2019
Kind
B2
Abstract

Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

Claims (46)

1. An apparatus to verify compressed data, the apparatus comprising:

at least one memory comprising instructions; and

logic coupled to the at least one memory, the instructions, when executed by the logic, to cause the logic to:

access compressed data,

access compression information associated with the compressed data,

divide the compressed data into a plurality of symbol segments,

provide the plurality of symbol segments to a plurality of decompressors to decompress the plurality of symbol segments in parallel to generate decompressed data, and

verify the compressed data via a comparison of the decompressed data with the compression information.

2. The apparatus of claim 1 , the compression process comprising one of an LZ77 compression process or a Deflate compression process.

3. The apparatus of claim 1 , the compression information comprising indicator information providing a length of symbols of the compressed data.

4. The apparatus of claim 1 , the compression information comprising indicator information providing a location of symbols of the compressed data.

5. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to divide the compressed data into the plurality of symbol segments based on at least one symbol location indicated by the compression information.

6. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to verify the compressed data by comparing at least one decompressed symbol size of the decompressed data with a corresponding symbol size of the compression information.

7. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to verify the compressed data by comparing at least one decompressed symbol location of the decompressed data with a corresponding symbol location of the compression information.

8. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to verify at least a portion of the decompressed data via a byte-by-byte comparison of the decompressed data with the compressed data.

9. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to generate debug information for the decompressed data, the debug information comprising at least one bit position of at least one decoded symbol of decompressed data.

10. The apparatus of claim 1 , the instructions, when executed by the logic, to cause the logic to:

generate debug information for the decompressed data, and

generate reconstructed compression information based on the debug information.

11. A computer-implemented method to verify compressed data, the method comprising, by a processor:

accessing compressed data;

accessing compression information associated with the compressed data;

dividing the compressed data into a plurality of symbol segments;

providing the plurality of symbol segments to a plurality of decompressors to decompress the plurality of symbol segments in parallel to generate decompressed data; and

verifying the compressed data via a comparison of the decompressed data with the compression information.

12. The computer-implemented method of claim 11 , the compression process comprising one of an LZ77 compression process or a Deflate compression process.

13. The computer-implemented method of claim 11 , the compression information comprising indicator information providing a length of symbols of the compressed data.

14. The computer-implemented method of claim 11 , the compression information comprising indicator information providing a location of symbols of the compressed data.

15. The computer-implemented method of claim 11 , comprising dividing the compressed data into a plurality of symbol segments based on at least one symbol location indicated by the compression information.

16. The computer-implemented method of claim 11 , comprising verifying the compressed data by comparing at least one decompressed symbol size of the decompressed data with a corresponding symbol size of the compression information.

17. The computer-implemented method of claim 11 , comprising verifying the compressed data by comparing at least one decompressed symbol location of the decompressed data with a corresponding symbol location of the compression information.

18. The computer-implemented method of claim 11 , comprising verifying at least a portion of the decompressed data via a byte-by-byte comparison of the decompressed data with the compressed data.

19. The computer-implemented method of claim 11 , comprising generating debug information for the decompressed data, the debug information comprising at least one bit position of at least one decoded symbol of decompressed data.

20. The computer-implemented method of claim 11 , comprising:

generating debug information for the decompressed data; and

generating reconstructed compression information based on the debug information.

21. A non-transitory computer-readable storage medium, comprising a plurality of instructions to verify compressed data that, when executed, enable processing circuitry to:

access compressed data;

access compression information associated with the compressed data;

divide the compressed data into a plurality of symbol segments;

provide the plurality of symbol segments to a plurality of decompressors to decompress the plurality of symbol segments in parallel to generate decompressed data; and

verify the compressed data via a comparison of the decompressed data with the compression information.

22. The non-transitory computer-readable storage medium of claim 21 , the compression information comprising indicator information providing a length of symbols of the compressed data.

23. The non-transitory computer-readable storage medium of claim 21 , the compression information comprising indicator information providing a location of symbols of the compressed data.

24. The non-transitory computer-readable storage medium of claim 21 , the plurality of instructions, when executed, enable the processing circuitry to divide the compressed data into a plurality of symbol segments based on at least one symbol location indicated by the compression information.

25. The non-transitory computer-readable storage medium of claim 21 , the plurality of instructions, when executed, enable the processing circuitry to decompress the at least a portion of the compressed data via a plurality of parsers in parallel to generate the decompressed data.

Continuity (2)
Continuation 15476945 · Mar 31, 2017
Related Publication 20180287630A1 · Oct 4, 2018