Clock generation for integrated circuit testing
A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.
1. An integrated circuit (IC) chip comprising:
a first clock generation circuit configured to:
receive a first clock signal having a first frequency; and
generate, in response to receipt of a first clock trigger signal and a first enable signal, a first set of clock pulses having the first frequency;
a second clock generation circuit configured to:
receive a second clock signal having a second frequency unequal to the first frequency; and
generate, in response to receipt of a second clock trigger signal and a second enable signal, a second set of clock pulses having the second frequency;
a stagger circuit coupled to receive a global trigger signal, wherein the stagger circuit is configured to generate the first and second clock trigger signals from the global trigger signal at different times, and the first set of clock pulses are staggered relative to the second set of clock pulses during a capture phase; and
a plurality of scan chains configured to test functionality of logic circuitry within the IC chip using the first and second sets of clock pulses.
2. The IC chip of claim 1 , wherein the stagger circuit includes a pipeline circuit coupled to receive the global trigger signal, and the pipeline circuit is configured to pass the global trigger signal between pipeline stages according to a third clock signal and generate the first and second clock trigger signals at different pipeline stages.
3. The IC chip of claim 1 , further comprising a pseudo-random pattern generator clocked by a third clock signal and configured to generate test data vectors that are provided to the plurality of scan chains.
4. The IC chip of claim 1 , further comprising an output shift register clocked by a third clock signal and configured to store test data vectors that are provided from the plurality of scan chains.
5. The IC chip of claim 1 , wherein the first and second clock generation circuits are connected to first and second multiplexers, respectively, the first multiplexer is configured to select between the first clock trigger signal and the global trigger signal for input to the first clock generation circuit, and the second multiplexer is configured to select between the second clock trigger signal and the global trigger signal for input to the second clock generation circuit.
6. The IC chip of claim 1 , wherein the first and second clock signals are asynchronous to each other.
7. The IC chip of claim 1 , wherein the first and second clock signals are synchronous to each other.
8. The IC chip of claim 1 , wherein the plurality of scan chains includes a first scan chain in a first clock domain and a second scan chain in a second clock domain, the first scan chain is coupled to receive the first set of clock pulses, the second scan chain is coupled to receive the second set of clock pulses.
9. The IC chip of claim 1 , wherein the stagger circuit further includes a decoder circuit, and the decoder circuit is configured and arranged to:
input a control signal; and
generate the first and second enable signals to the first and second clock generation circuits in response to the control signal;
wherein:
the first clock generation circuit is configured to generate the first set of clock pulses in response to a first state of the first enable signal and not generate the first set of clock pulses in response to a second state of the first enable signal; and
the second clock generation circuit is configured to generate the second set of clock pulses in response to a first state of the second enable signal and not generate the second set of clock pulses in response to a second state of the second enable signal.
10. The IC chip of claim 1 , wherein the stagger circuit further includes a decoder circuit, and the decoder circuit is configured and arranged to:
input a control signal; and
generate a stagger enable signal in response to the control signal;
wherein the stagger circuit is further configured and arranged to generate the first and second clock trigger signals from the global trigger signal at different times in response to a first state of the stagger enable signal, and to generate the first and second clock trigger signals from the global trigger signal at the same time in response to a second state of the stagger enable signal.
11. A method for use with an integrated circuit (IC) chip, the method comprising:
using a first clock generation circuit to:
receive a first clock signal having a first frequency; and
generate, in response to receipt of a first clock trigger signal and a first enable signal, a first set of clock pulses having the first frequency;
using a second clock generation circuit to:
receive a second clock signal having a second frequency unequal to the first frequency; and
generate, in response to receipt of a second clock trigger signal and a second enable signal, a second set of clock pulses having the second frequency;
generating, using a stagger circuit that inputs a global trigger signal, the first and second clock trigger signals from the global trigger signal at different times;
staggering the first and second sets of clock pulses during a capture phase in response to the first and second clock trigger signals; and
testing functionality of logic circuitry within the IC chip using a plurality of scan chains and the first and second sets of clock pulses.
12. The method of claim 11 , further comprising:
passing the global trigger signal between pipeline stages of a pipeline circuit; and
providing the first and second clock trigger signals from different ones of the pipeline stages.
13. The method of claim 11 , further comprising clocking a pseudo-random pattern generator ( 116 ) by a third clock signal to generate test data vectors that are provided to the plurality of scan chains.
14. The method of claim 11 , further comprising clocking an output shift register by a third clock signal to store test data vectors that are provided from the plurality of scan chains.
15. The method of claim 11 , further comprising:
selecting, using a first multiplexer connected to the first clock generation circuit, between the first clock trigger signal and the global trigger signal; and
selecting, using a second multiplexer connected to the second clock generation circuit, between the second clock trigger signal and the global trigger signal.
16. The method of claim 11 , wherein the first and second clock signals are asynchronous to each other.
17. The method of claim 11 , wherein the first and second clock signals are synchronous to each other.
18. The method of claim 11 , wherein the plurality of scan chains includes a first scan chain in a first clock domain and a second scan chain in a second clock domain, and the method further comprising applying the first set of clock pulses to the first scan chain, and applying the second set of clock pulses to the second scan chain.
19. The method of claim 11 , wherein the stagger circuit further includes a decoder circuit, the method further comprising:
inputting a control signal to the decoder circuit; and
generating the first and second enable signals to the first and second clock generation circuits in response to the control signal;
wherein:
the generating the first set of clock pulses includes generating the first set of clock pulses in response to a first state of the first enable signal and not generating the first set of clock pulses in response to a second state of the first enable signal; and
the generating the second set of clock pulses includes generating the second set of clock pulses in response to a first state of the second enable signal and not generate the second set of clock pulses in response to a second state of the second enable signal.
20. The method of claim 11 , wherein the stagger circuit further includes a decoder circuit, and the method further comprising:
inputting a control signal to the decoder circuit;
generating a stagger enable signal in response to the input control signal; and
generating by the stagger circuit, the first and second clock trigger signals from the global trigger signal at different times in response to a first state of the stagger enable signal, and generating the first and second clock trigger signals from the global trigger signal at the same time in response to a second state of the stagger enable signal.