Gallium nitride nanowire based electronics
GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.
1. A method of fabricating a nitride semiconductor wafer comprising the steps of:
forming nanowires without threading dislocations on a substrate surface;
forming nitride semiconductor nanostructures without threading dislocations by growing respective nitride semiconductor volume elements from the nanowires;
planarizing the nitride semiconductor volume elements of the nitride semiconductor nanostructures to form separated individual mesas having exposed planar c-plane upper surfaces; and
epitaxially growing a respective planar stoichiometric nitride semiconductor layer on the planar c-plane upper surfaces of the separated individual mesas, such that at least 90% of the planar nitride semiconductor layers have no threading dislocations and a flat c-plane surface.
2. The method of claim 1 , wherein the step of forming nitride semiconductor nanostructures comprises:
providing a growth mask with openings on the substrate surface; and
forming the nanowires by selectively growing an array of strain-relaxed nitride semiconductor nanowires from the apertures, wherein threading dislocations are rejected from the nanowire in an early stage of nanowire growth.
3. The method of claim 2 , wherein the nitride semiconductor volume element comprises a GaN volume element grown at conditions similar to planar GaN.
4. The method according to claim 1 , wherein the step of planarization is made through temperature assisted anisotropic etching.
5. The method according to claim 1 , wherein the step of planarization is made in situ.
6. The method according to claim 1 , wherein 90-99% of the at least planar stoichiometric nitride semiconductor layers do not have threading dislocations.
7. The method of claim 2 , wherein the substrate comprises a buffer layer and the nanowire growth limits the protrusion of crystal dislocations from the nanowire/buffer layer interface.
8. The method of claim 7 , wherein the buffer layer comprises GaN or AlGaN.
9. The method of claim 7 , wherein the buffer layer comprise a thin film of AlN, Al 2 O 3 , graphene or diamond.
10. The method of claim 2 , wherein the substrate provides electrical insulation between the separated individual mesas, resulting in a partitioned wafer.
11. The method of claim 1 , wherein at least a part of the substrate is removed and replaced by a handle substrate.
12. The method of claim 11 , wherein the handle substrate comprise heat conductive material.
13. The method of claim 12 , wherein the conductive material comprises Al, Cu or graphene.
14. The method of claim 1 , wherein the respective nitride semiconductor volume elements are grown from a side of the nanowires.
15. The method of claim 1 , wherein the planar stoichiometric nitride semiconductor layers are also grown on pyramidal side facets of the separated individual mesas.