Selective deposition utilizing sacrificial blocking layers for semiconductor devices
Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
1. A semiconductor device, comprising:
a semiconductor structure disposed above a semiconductor substrate;
an isolation sidewall disposed beside the semiconductor structure and above the semiconductor substrate;
a high-K dielectric layer disposed directly on more than one side of the semiconductor structure and not disposed along the isolation sidewall, wherein the high-K dielectric layer comprises a metal; and
a shallow trench isolation (STI) disposed directly on top of the semiconductor substrate, wherein the high-K dielectric layer is also disposed on the STI, wherein the high-K dielectric layer includes tapered or rounded ends disposed adjacent to the isolation sidewall, the high-K dielectric layer does not contact the isolation sidewall.
2. The semiconductor device of claim 1 , further comprising a gate electrode disposed on the high-K dielectric layer and on a portion of the isolation sidewall.
3. The semiconductor device of claim 2 , further comprising a molecular fragment layer disposed between the gate electrode and the isolation layer.
4. The semiconductor device of claim 3 , wherein the molecular fragment layer comprises a dangling bond formed of at least one of a phosphorous, carbon, oxygen, nitrogen, sulfur, silicon, or chlorine atom.
5. The semiconductor device of claim 1 , wherein the semiconductor structure is a fin that extends upward from the semiconductor substrate.
6. The semiconductor device of claim 5 , wherein the more than one side includes a top surface of the fin and a portion of each sidewall of the fin.
7. A semiconductor device, comprising:
a semiconductor structure disposed above a semiconductor substrate;
an isolation sidewall disposed beside the semiconductor structure and above the semiconductor substrate;
a high-K dielectric layer disposed directly on more than one side of the semiconductor structure and not disposed on the isolation sidewall; and
a shallow trench isolation (STI) disposed directly on top of the semiconductor substrate, wherein the high-K dielectric layer includes tapered or rounded ends disposed immediately above the STI, the high-K dielectric layer does not contact the STI.
8. A method of forming a semiconductor device, comprising:
providing a semiconductor structure disposed above a semiconductor substrate, the semiconductor structure disposed beside an isolation sidewall;
depositing a sacrificial blocking layer on at least the isolation sidewall, exposing the semiconductor structure;
subsequent to depositing the sacrificial blocking layer, depositing a high-K dielectric layer on the semiconductor structure; and
removing the sacrificial blocking layer.
9. A method of forming a semiconductor device, comprising:
providing a semiconductor structure disposed above a semiconductor substrate, the semiconductor structure disposed beside an isolation sidewall;
depositing a sacrificial blocking layer on at least the isolation sidewall, exposing the semiconductor structure;
depositing a high-K dielectric layer on the semiconductor structure; and
removing the sacrificial blocking layer, wherein the sacrificial blocking layer is a self-assembled monolayer (SAM).
10. The method of claim 9 , wherein the SAM is formed of molecules that are capable of blocking formation of the high-K dielectric layer on the isolation sidewalls.
11. The method of claim 10 , wherein the molecules are molecules selected from the group consisting of octadecylphophonic acide (ODPA), 1-octadecanethiol (ODT), octadecyltrichlorsilane (ODTCS), and stearic acid (ODCA).
12. A method of forming a semiconductor device, comprising:
providing a semiconductor structure disposed above a semiconductor substrate, the semiconductor structure disposed beside an isolation sidewall;
depositing a sacrificial blocking layer on at least the isolation sidewall, exposing the semiconductor structure;
depositing a high-K dielectric layer on the semiconductor structure; and
removing the sacrificial blocking layer, wherein removing the sacrificial blocking layer comprises a thermal treatment or a chemical treatment.
13. The method of claim 12 , wherein the thermal treatment is performed at a decomposition temperature greater than a deposition temperature of the dielectric layer.
14. The method of claim 12 , wherein the chemical treatment comprises exposure to a base solution comprising tetramethylammonium hydroxide (TMAH).
15. A method of forming a semiconductor device, comprising:
providing a semiconductor structure disposed above a semiconductor substrate, the semiconductor structure disposed beside an isolation sidewall;
depositing a sacrificial blocking layer on at least the isolation sidewall, exposing the semiconductor structure;
depositing a high-K dielectric layer on the semiconductor structure; and
removing the sacrificial blocking layer, wherein removing the sacrificial blocking layer results in a molecular fragment layer disposed on at least the isolation layer.
16. The method of claim 15 , wherein the molecular fragment layer comprises an atom selected from the group consisting of phosphorous, carbon, nitrogen, sulfur, silicon, and chlorine.
17. A method of forming a semiconductor device, comprising:
providing a semiconductor structure disposed above a semiconductor substrate, the semiconductor structure disposed beside an isolation sidewall;
depositing a sacrificial blocking layer on at least the isolation sidewall, exposing the semiconductor structure;
depositing a high-K dielectric layer on the semiconductor structure; and
removing the sacrificial blocking layer, wherein depositing the high-K dielectric layer is performed at an oxide deposition temperature, wherein the oxide deposition temperature is less than the decomposition temperature of the sacrificial blocking layer.
18. A computing device, comprising:
a motherboard;
a processor mounted on the motherboard; and a communication chip fabricated on the same chip as the processor or mounted on the motherboard;
wherein the processor comprises:
a semiconductor structure disposed above a semiconductor substrate;
a shallow trench isolation (STI) disposed directly on top of the semiconductor substrate;
an isolation sidewall disposed beside the semiconductor structure and on the STI;
a high-K dielectric layer disposed directly on more than one side of the semiconductor structure and not along the isolation sidewall, wherein the high-K dielectric layer comprises a metal; and
a shallow trench isolation (STI) disposed directly on top of the semiconductor substrate, wherein the high-K dielectric layer includes tapered or rounded ends disposed immediately above the STI, and wherein the high-K dielectric layer does not contact the STI.
19. The computing device of claim 18 , further comprising a gate electrode disposed on the high-K dielectric layer and on a portion of the isolation sidewall.
20. The computing device of claim 19 , further comprising a molecular fragment layer disposed between the gate electrode and the isolation layer.