System and method for a switch transistor driver
In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.
1. A switched-mode power supply (SMPS) comprising:
an insulated-gate bipolar transistor (IGBT); and
a gate driver circuit having an input configured to receive a gate signal and an output coupled to a gate of the IGBT, the gate driver circuit comprising:
a random signal generator coupled to the input of the gate driver circuit, and
a first circuit comprising a plurality of high-side transistors and a plurality of low-side transistors, the first circuit coupled to the random signal generator and configured to adjust a drive strength of the output of the gate driver circuit based on an output of the random signal generator,
wherein two of the plurality of high-side transistors have gates coupled to different outputs of the random signal generator,
wherein the plurality of high-side transistors are configured to be deactivated when one-or-more low-side transistors of the plurality of low-side transistors is activated, and
wherein the plurality of low-side transistors are configured to be deactivated when one-or-more high-side transistors of the plurality of high-side transistors is activated.
2. The SMPS of claim 1 , wherein the random signal generator generates a new random signal every cycle of the gate signal.
3. The SMPS of claim 1 , wherein the random signal generator generates a new signal at the output of the random signal generator each cycle of the gate signal.
4. The SMPS of claim 1 , wherein:
the plurality of high-side transistors is coupled between the output of the gate driver circuit and a first supply terminal, each of the plurality of high-side transistors having a control terminal coupled to a respective output of the random signal generator; and
the plurality of low-side transistors is coupled between the output of the gate driver circuit and a second supply terminal, each of the plurality of low-side transistors having a control terminal coupled to a respective output of the random signal generator.
5. The SMPS of claim 4 , wherein the random signal generator is configured to independently select transistors from the plurality of high-side transistors; and independently select transistors from the plurality of low-side transistors.
6. The SMPS of claim 4 , wherein each of the plurality of high-side transistors form a transistor pair with a respective transistor of the plurality of low-side transistors to form a plurality of pairs of transistors; and the random signal generator is configured to randomly select a subset of pairs of transistors.
7. An integrated circuit comprising:
an input terminal configured to receive a gate signal;
a first output terminal configured to be coupled to a control terminal of a switching transistor;
a random signal generator having a plurality of outputs; and
a first circuit configured to generate an output signal at the first output terminal based on the gate signal and with a drive strength based on the plurality of outputs of the random signal generator, the first circuit comprising a plurality of high-side transistors and a plurality of low-side transistors,
wherein two of the plurality of low-side transistors have gates coupled to different outputs of the plurality of outputs of the random signal generator,
wherein the plurality of high-side transistors are configured to be deactivated when one-or-more low-side transistors of the plurality of low-side transistors is activated, and
wherein the plurality of low-side transistors are configured to be deactivated when one-or-more high-side transistors of the plurality of high-side transistors is activated.
8. The integrated circuit of claim 7 , further comprising the switching transistor, wherein the switching transistor is an insulated-gate bipolar transistor.
9. The integrated circuit of claim 7 , wherein the random signal generator updates the plurality of outputs of the random signal generator each cycle of the gate signal.
10. The integrated circuit of claim 7 , further comprising a second output terminal configured to be coupled to the control terminal of the switching transistor, wherein:
the plurality of high-side transistors is coupled between the first output terminal a first supply terminal, each of the plurality of high-side transistors having a control terminal coupled to a respective output of the plurality of outputs of the random signal generator; and
the plurality of low-side transistors is coupled between the second output terminal and a second supply terminal, each of the plurality of low-side transistors having a control terminal coupled to a respective output of the plurality of outputs of the random signal generator.
11. The integrated circuit of claim 10 , wherein the first output terminal is coupled to the second output terminal to form a first node, the first node coupled to the control terminal of the switching transistor via a first resistor.
12. The integrated circuit of claim 7 , further comprising a second output terminal configured to be coupled to the control terminal of the switching transistor, wherein the first circuit comprises:
a first transistor coupled between a first supply terminal and the first output terminal;
a second transistor coupled between the first output terminal and a second supply terminal;
a third transistor coupled between the first supply terminal and the second output terminal; and
a fourth transistor coupled between the second output terminal and the second supply terminal, wherein the first, second, third, and fourth transistors has a control terminal coupled to a respective output of the plurality of outputs of the random signal generator.
13. The integrated circuit of claim 12 , wherein the first output terminal is configured to be coupled to the control terminal of the switching transistor via a first resistor; and
the second output terminal is configured to be coupled to the switching transistor via a second resistor.
14. The integrated circuit of claim 7 , wherein the random signal generator comprises:
a random number generator coupled to the input terminal; and
a lookup table coupled between the random number generator and the plurality of outputs of the random signal generator via a logic circuit, the logic circuit coupled to the input terminal.
15. The integrated circuit of claim 14 , wherein the random number generator comprises a linear feedback shift register.
16. The integrated circuit of claim 15 , wherein the linear feedback shift register comprises 16 D-flip-flops.
17. The integrated circuit of claim 14 , wherein the random number generator comprises a hardware generator based on thermal noise, shot noise, avalanche noise, or radioactive decay.
18. A method for attenuating peaks in a spectrum of electromagnetic interference (EMI), the method comprising:
receiving a gate signal, the gate signal switching between a first state and a second state;
generating a plurality of sets of random values with a random signal generator; and
driving a control node of a switching transistor with a plurality of high-side transistors and a plurality of low-side transistors based on the gate signal and with a drive strength based on a set of the plurality of sets of random values, wherein a new set of the plurality of sets of random values is generated each cycle of the gate signal, and
wherein two of the plurality of high-side transistors have gates coupled to different outputs of the random signal generator;
deactivating the plurality of high-side transistors when one-or-more low-side transistors of the plurality of low-side transistors is activated; and
deactivating the plurality of low-side transistors when one-or-more high-side transistors of the plurality of high-side transistors is activated.
19. The method of claim 18 , further generating the plurality of sets of random values is based on thermal noise, shot noise, avalanche noise, or radioactive noise.
20. The SMPS of claim 1 , wherein the plurality of high-side transistors and the plurality of low-side transistors are directly connected to the gate of the IGBT via a passive component.
21. The SMPS of claim 20 , wherein the plurality of high-side transistors and the plurality of low-side transistors are directly connected to the gate of the IGBT via respective passive component.
22. The SMPS of claim 20 , wherein the passive component comprises a resistor.