IP Library Granted Patent US 10,249,575
Granted Patent B2
US 10,249,575 · App. 15/792,544 · Granted Apr 2, 2019

Radio-frequency isolation using cavity formed in interface layer

Inventors: David T. Petzold (Chelmsford, MA); David Scott Whitefield (Andover, MA)
Assignee: Skyworks Solutions, Inc.
H01L23/562H01L21/30604H01L21/6835H01L21/764H01L21/768H01L21/76251H01L21/76802H01L21/76877H01L21/76895H01L21/76898H01L21/84H01L23/5283H01L23/535H01L23/66H01L27/1203H01L27/20H01L28/10H01L29/0649H01L29/66772H01L29/78H01L29/786H03H9/02566H03H9/24H04B1/40H04B1/44H01L23/3121H01L24/05H01L24/06H01L24/48H01L24/73H01L25/16H01L2221/6834H01L2221/68318H01L2221/68327H01L2221/68359H01L2221/68368H01L2223/6677H01L2224/03H01L2224/03002H01L2224/04042H01L2224/05554H01L2224/06135H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/94H01L2924/00014H01L2924/1306H01L2924/1421H01L2924/15192H01L2924/15313
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Quick Facts
Patent No.
US 10,249,575
App. No.
15/792,544
Granted
Apr 2, 2019
Kind
B2
Abstract

A method for fabricating a semiconductor device involves providing a transistor device, forming one or more electrical connections to the transistor device, forming one or more dielectric layers over at least a portion of the electrical connections, applying an interface material over at least a portion of the one or more dielectric layers, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

Claims (35)

1. A method for fabricating a semiconductor device, the method comprising:

providing a transistor device;

forming one or more electrical connections to the transistor device;

forming one or more dielectric layers over at least a portion of the electrical connections;

applying an interface material over at least a portion of the one or more dielectric layers;

removing at least a portion of the interface material to form a trench; and

covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

2. The method of claim 1 further comprising disposing an electrical element over the one or more dielectric layers, the electrical element being disposed at least partially within the cavity.

3. The method of claim 2 wherein the electrical element is a surface acoustic wave (SAW) device.

4. The method of claim 2 wherein the electrical element is a bulk acoustic wave (BAW) device.

5. The method of claim 1 wherein the transistor device is formed over a semiconductor substrate and an oxide layer formed on the semiconductor substrate.

6. The method of claim 5 further comprising at least partially removing the semiconductor substrate thereby exposing at least a portion of a backside of the oxide layer.

7. The method of claim 6 further comprising disposing an electrical contact structure on the backside of the oxide layer to provide electrical contact to the one or more electrical connections via a through-oxide via.

8. A semiconductor device comprising:

a transistor device implemented over a semiconductor substrate;

one or more dielectric layers formed over at least a portion of the transistor device;

an interface layer covering at least a portion of the one or more dielectric layers, the interface layer having a trench therein; and

a substrate layer covering at least a portion of the interface layer and the trench to form a cavity.

9. The semiconductor device of claim 8 further comprising an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor device via one or more electrical connections disposed at least partially in the one or more dielectric layers.

10. The semiconductor device of claim 9 wherein the electrical element is a surface acoustic wave (SAW) device.

11. The semiconductor device of claim 9 wherein the electrical element is a bulk acoustic wave (BAW) device.

12. The semiconductor device of claim 9 wherein the electrical element is a passive device.

13. The semiconductor device of claim 8 wherein the transistor device is formed over an oxide layer.

14. A semiconductor die comprising:

a semiconductor substrate;

a transistor device implemented over the semiconductor substrate;

one or more dielectric layers formed over at least a portion of the transistor device;

an interface layer covering at least a portion of the one or more dielectric layers and having a trench therein; and

a substrate layer covering at least a portion of the interface layer and the trench to form a cavity.

15. The semiconductor die of claim 14 further comprising an electrical element disposed over the one or more dielectric layers that is electrically coupled to the transistor device via one or more electrical connections disposed at least partially within the one or more dielectric layers.

16. The semiconductor die of claim 15 wherein the electrical element is a surface acoustic wave (SAW) device.

17. The semiconductor die of claim 15 wherein the electrical element is a bulk acoustic wave (BAW) device.

18. The semiconductor die of claim 15 wherein the electrical element is a passive device.

19. The semiconductor die of claim 15 wherein the electrical element is an inductor.

20. The semiconductor die of claim 14 further comprising an electrical contact structure disposed on a backside of an oxide layer formed between the semiconductor substrate and the transistor device, the electrical contact structure providing electrical contact to the transistor device via a through-oxide via.

Continuity (3)
Continuation 15154777 · May 13, 2016
Provisional Application 62162643 · May 15, 2015
Related Publication 20180076791A1 · Mar 15, 2018