Transistor with source field plates and non-overlapping gate runner layers
A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
1. A device, comprising:
a semiconductor substrate having a top surface defining a channel region, the channel region having first and second dimensions parallel to said top surface, said second dimension deviating from said first dimension;
a source contact layer contacting the top surface;
a gate layer above the channel region;
a source field plate extending from the source contact layer over the gate layer along the first dimension;
a gate runner layer coextending with the source field plate along the second dimension, and
a gate bridge extending from the gate layer, across the source contact layer, and under the gate runner layer, the gate bridge coupled between the gate layer and the gate runner layer.
2. The device of claim 1 , further comprising:
an insulation layer positioned between the gate bridge and the top surface.
3. The device of claim 2 , wherein the gate bridge and the gate layer share a common metal layer having a higher resistivity than the gate runner layer.
4. The device of claim 3 , wherein the common metal layer includes a titanium tungsten material.
5. The device of claim 1 , wherein the source field plate is coplanar with the gate runner layer, and the source field plate has a lower resistivity than the source contact layer.
6. The device of claim 1 , wherein the source field plate is coplanar with the source contact layer, and the source field plate has a higher resistivity than the gate runner layer.
7. The device of claim 1 , wherein the source contact layer includes an aluminum-copper-titanium alloy.
8. The device of claim 1 , wherein the semiconductor substrate includes a gallium nitride layer contacted by the source contact layer.
9. The device of claim 1 , wherein the source field plate is a first source field plate, and further comprising:
a second source field plate above the first source field plate and extending along the first dimension farther away from the source contact layer than the first source field plate and overlapping the gate runner layer.
10. The device of claim 1 , wherein the first dimension is perpendicular to the second dimension.
11. A transistor, comprising:
a semiconductor substrate having a top surface defining a channel region;
a source contact layer contacting a first end of the channel region;
a drain contact layer contacting a second end of the channel region;
a gate layer above the channel region and closer to the source contact layer than the drain contact layer;
a source field plate extending from the source contact layer along a first dimension of the channel region and over the gate layer;
a gate runner layer coextending with the source field plate along a second dimension of the channel region perpendicular to the first dimension; and
a gate bridge extending from the gate layer, across the source contact layer, and under the gate runner layer, the gate bridge coupled between the gate layer and the gate runner layer.
12. The transistor of claim 11 , wherein the source contact layer is interposed between the gate layer and the gate runner layer along the first dimension.
13. The device of claim 11 , wherein the source field plate is coplanar with the gate runner layer, and the source field plate has a lower resistivity than the source contact layer.
14. The device of claim 11 , wherein the source field plate is coplanar with the source contact layer, and the source field plate has a higher resistivity than the gate runner layer.
15. The transistor of claim 11 , wherein the source field plate is a first source field plate, and further comprising:
a second source field plate above the first source field plate and extending along the first dimension farther away from the source contact layer than the first source field plate and overlapping the gate runner layer.
16. An integrated circuit, comprising:
a semiconductor substrate having a top surface; and
transistors, each including:
a channel region defined on the top surface;
a source contact layer contacting a first end of the channel region;
a drain contact layer contacting a second end of the channel region;
a gate layer above the channel region and closer to the source contact layer than the drain contact layer;
a source field plate extending above the source contact layer along a first dimension of the channel region and over the gate layer;
a gate runner layer coextending with the source field plate along a second dimension of the channel region perpendicular to the first dimension; and
a gate bridge extending from the gate layer, across the source contact layer, and under the gate runner layer, the gate bridge coupled between the gate layer and the gate runner layer.
17. The transistor of claim 16 , wherein the source contact layer is interposed between the gate layer and the gate runner layer along the first dimension.
18. The device of claim 16 , wherein the source field plate is coplanar with the gate runner layer, and the source field plate has a lower resistivity than the source contact layer.
19. The device of claim 16 , wherein the source field plate is coplanar with the source contact layer, and the source field plate has a higher resistivity than the gate runner layer.
20. The transistor of claim 16 , wherein the source field plate is a first source field plate, and further comprising:
a second source field plate above the first source field plate and extending along the first dimension farther away from the source contact layer than the first source field plate and overlapping the gate runner layer.