Semiconductor device and method of manufacturing the same
An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.
1. A semiconductor device, comprising:
a semiconductor substrate; and
a first buffer layer being formed in one main surface at one side of the semiconductor substrate which is closer to the first buffer layer than another main surface at an opposite side of the semiconductor substrate and having a plurality of peaks of concentration of protons whose depths from the one main surface are different from each other, wherein
in the first buffer layer, a concentration gradient of the protons from one of the plurality of peaks located in a position closer to the one main surface toward the another main surface of the semiconductor substrate is smaller than a concentration gradient of the protons from another one of the plurality of peaks located in a position farther away from the one main surface toward the another main surface.
2. The semiconductor device according to claim 1 , wherein
each of the concentration gradients of the protons from each of the plurality of peaks toward the another main surface is equal to or smaller than 2.0E14 cm 3 /μm.
3. The semiconductor device according to claim 1 , wherein
in the first buffer layer, the concentration of the protons in a region located closer to the one main surface than the another main surface is equal to or smaller than an impurity concentration of the semiconductor substrate.
4. The semiconductor device according to claim 1 , wherein
in the first buffer layer, each of the plurality of peaks of the concentration of the protons becomes smaller from the one main surface toward the another main surface of the semiconductor substrate.
5. The semiconductor device according to claim 1 , wherein
the first buffer layer includes three or more peaks of the concentration of the protons.
6. The semiconductor device according to claim 1 , wherein
the first buffer layer has a depth equal to or larger than 20 μm from the one main surface.
7. The semiconductor device according to claim 1 , further comprising
a second buffer layer formed in the one main surface at the one side of the semiconductor substrate.
8. The semiconductor device according to claim 7 , wherein
an impurity of the second buffer layer is made of phosphorus or arsenic.
9. A method of manufacturing the semiconductor device according to claim 8 , wherein
the first buffer layer is formed by activating the protons by a furnace annealing, and
the second buffer layer is formed by activating the phosphorus or the arsenic by a laser annealing.
10. The semiconductor device according to claim 1 , wherein
the semiconductor device is an insulated gate bipolar transistor or a diode.
11. A method of manufacturing the semiconductor device according to claim 1 , wherein
the first buffer layer is formed by implanting ions several times, using an ion implanter, with different acceleration voltages of 1.5 MeV or smaller at different implantation angles.
12. A method of manufacturing the semiconductor device according to claim 1 , wherein
the first buffer layer is formed by implanting ions several times, using an ion implanter, with a shield which shields a region where the first buffer layer is to be formed in the one main surface of the semiconductor substrate in between with different acceleration voltages of 1.5 MeV or smaller.
13. A semiconductor device, comprising:
a semiconductor substrate; and
a first buffer layer being formed in one main surface at one side of the semiconductor substrate which is closer to the first buffer layer than another main surface at an opposite side of the semiconductor substrate and having a plurality of peaks of concentration of protons whose depths from the one main surface are different from each other, wherein
in the first buffer layer, a half value width of one of the plurality of peaks located in a position closer to the one main surface is larger than a half value width of another one of the plurality of peaks located in a position farther away from the one main surface.
14. The semiconductor device according to claim 13 , wherein
each of the half value widths of each of the plurality of peaks is equal to or larger than 1.0 μM.
15. The semiconductor device according to claim 13 , wherein
in the first buffer layer, a concentration of the protons in a region located closer to the one main surface than the another main surface is equal to or smaller than an impurity concentration of the semiconductor substrate.
16. The semiconductor device according to claim 13 , wherein
in the first buffer layer, each of the plurality of peaks of the concentration of the protons becomes smaller from the one main surface toward the another main surface of the semiconductor substrate.
17. The semiconductor device according to claim 13 , wherein
the first buffer layer includes three or more peaks of the concentration of the protons.
18. The semiconductor device according to claim 13 , wherein
the first buffer layer has a depth equal to or larger than 20 μm from the one main surface.
19. The semiconductor device according to claim 13 further comprising
a second buffer layer formed in the one main surface at the one side of the semiconductor substrate.
20. The semiconductor device according to claim 19 , wherein
an impurity of the second buffer layer is made of phosphorus or arsenic.
21. A method of manufacturing the semiconductor device according to claim 20 , wherein
the first buffer layer is formed by activating the protons by a furnace annealing, and
the second buffer layer is formed by activating the phosphorus or the arsenic by a laser annealing.
22. The semiconductor device according to claim 13 , wherein
the semiconductor device is an insulated gate bipolar transistor or a diode.
23. A method of manufacturing the semiconductor device according to claim 13 , wherein
the first buffer layer is formed by implanting ions several times, using an ion implanter, with different acceleration voltages of 1.5 MeV or smaller at different implantation angles.
24. A method of manufacturing the semiconductor device according to claim 13 , wherein
the first buffer layer is formed by implanting ions several times, using an ion implanter, with a shield which shields a region where the first buffer layer is to be formed in the one main surface of the semiconductor substrate in between with different acceleration voltages of 1.5 MeV or smaller.