Multiplexed multi-stage low noise amplifier uses gallium arsenide and CMOS dice
A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.
1. A mixed technology Low Noise Amplifier (LNA), the LNA comprised of:
an external bias control; coupled to,
a gate voltage bias circuit, which mirrors its gate voltage to,
a multi-stage pHEMPT amplifier (GaAs) module;
a final CMOS stage amplifier;
a first parallel pHEMPT stage amplifier coupled in series to a first signal source, and to a first switchable control voltage connector;
a second parallel pHEMPT stage amplifier coupled in series to a second signal source, and to a second switchable control voltage connector;
a penultimate pHEMPT stage amplifier coupled to a plurality of parallel pHEMPT stage amplifiers, and to a penultimate switchable control voltage connector; and
a single-pole-double-throw switch coupled to the first and second switchable control voltage connectors, whereby the circuit emits one of the group an amplified first signal, and an amplified second signal when the penultimate switchable control voltage enables emission.
2. A mixed technology Low Noise Amplifier (LNA), the LNA comprised of:
an external bias control; coupled to,
a gate voltage bias circuit, which mirrors its gate voltage to,
a multi-stage pHEMPT amplifier (GaAs) module;
wherein the gate voltage bias circuit comprises:
a transistor having a gate terminal, a drain terminal, and a source terminal; the transistor coupled its gate terminal to a gate terminal of
an amplifier transistor through at least one pass transistor of at least one stage amplifier and through an input impedance matching network, whereby a current mirror provides a gate bias voltage value to each stage amplifier; the gate terminal of the transistor further coupled through a diode circuit to a temperature compensation current source and to its drain terminal; the gate terminal of the transistor further coupled through a resistor to negative voltage; and the gate voltage bias circuit further coupled to ground at its source terminal.
3. A mixed technology Low Noise Amplifier (LNA), the LNA comprised of:
an external bias control; coupled to,
a gate voltage bias circuit, which mirrors its gate voltage to,
a multi-stage pHEMPT amplifier (GaAs) module;
wherein each pHEMPT stage amplifier comprises:
a pHEMPT amplifier transistor having a gate terminal a drain terminal and a source terminal the pHEMPT amplifier transistor coupled to ground at its source terminal and coupled to an output impedance matching network (Zout) at its drain terminal;
a pass transistor having a gate terminal, a drain terminal, and a source terminal; the pass transistor coupled at its source terminal to the gate terminal of the pHEMPT amplifier transistor by an input impedance matching network (Zin) and coupled at its drain terminal to a gate terminal of the gate voltage bias circuit; said input impedance matching network (Zin) of the stage amplifier further coupled to an amplifier input connector; the pass transistor further coupled at its gate terminal to a control voltage connector and through a diode circuit to its source terminal; and the output impedance matching network Zout further coupled to Vcc and to an amplifier output connector.