Programming NAND flash with improved robustness against dummy WL disturbance
A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.
1. A memory comprising:
a plurality of memory cells arranged in series in a semiconductor body;
a first string select switch between a reference line and a first end of the plurality of memory cells, and a second string select switch between a bit line and a second end of the plurality of memory cells;
first and second dummy memory cells arranged in series between the first string select switch and a first edge memory cell at the first end or between the second string select switch and a second edge memory cell at the second end, the first dummy memory cell being adjacent one of the first and second edge memory cells, the second dummy memory cell being adjacent one of the first and second string select switches;
a channel line including channels for the memory cells in the plurality of memory cells and the first and second dummy memory cells;
a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and
control circuitry coupled to the plurality of word lines and the first and second dummy memory cells adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
applying a switching voltage to the first dummy memory cell, the switching voltage stepping up to a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level during a second time interval; and
during a third time interval, applying a program voltage to the selected word line, while keeping the second voltage level on the first dummy memory cell.
2. The memory of claim 1 , comprising:
during the first time interval, pre-charging the bit line coupled to the channel line.
3. The memory of claim 2 , when the bit line is pre-charged and a memory cell in the plurality of memory cells is at a high threshold voltage blocking a pre-charge current through the channel line, a transition of the switching voltage to the first voltage level during the first time interval causes a boosted potential in a part of the channel line beneath the first dummy memory cell.
4. The memory of claim 1 , comprising:
during the first time interval, applying a pass voltage level to the second dummy memory cell; and
during the second and third time intervals, keeping the pass voltage level on the second dummy memory cell.
5. The memory of claim 1 , comprising:
during the first time interval, applying a blocking voltage lower than the first voltage level to the selected word line.
6. The memory of claim 1 , comprising:
during the first time interval, applying a blocking voltage to unselected word lines corresponding to unselected memory cells in the plurality of memory cells;
during the second time interval, applying a pass voltage to the unselected word lines and the selected word line, the pass voltage being lower than the program voltage; and
during the third time interval, keeping the pass voltage on the unselected word lines.
7. The memory of claim 1 , comprising a continuous charge trapping structure between the channel line and dummy word lines corresponding to the first and second dummy memory cells.
8. The memory of claim 1 , comprising:
a third dummy memory cell arranged in series between the first and second dummy memory cells; and
the control circuitry coupled to the third dummy memory cell and further adapted for programming the selected memory cell by:
during the first time interval, applying a pass voltage level to the third dummy memory cell; and
during the second and third time intervals, keeping the pass voltage level on the third dummy memory cell.
9. The memory of claim 8 , the channel line including a channel for the third dummy memory cell.
10. A method for programming a selected memory cell in a plurality of memory cells arranged in series in a memory device, the memory device including:
a first string select switch between a reference line and a first end of the plurality of memory cells, and a second string select switch between a bit line and a second end of the plurality of memory cells;
first and second dummy memory cells arranged in series between the first string select switch and a first edge memory cell at the first end or between the second string select switch and a second edge memory cell at the second end, the first dummy memory cell being adjacent one of the first and second edge memory cells, the second dummy memory cell being adjacent one of the first and second string select switches; and
a channel line including channels for the memory cells in the plurality of memory cells and the first and second dummy memory cells,
the method comprising:
applying a switching voltage to the first dummy memory cell, the switching voltage stepping up to a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level; and
during a third time interval, applying a program voltage to a selected word line corresponding to the selected memory cell, while keeping the second voltage level on the first dummy memory cell.
11. The method of claim 10 , comprising:
during the first time interval, pre-charging the bit line coupled to the channel line.
12. The method of claim 11 , when the bit line is pre-charged and a memory cell in the plurality of memory cells is at a high threshold voltage blocking a pre-charge current through the channel line, a transition of the switching voltage to the first voltage level during the first time interval causes a boosted potential in a part of the channel line beneath the first dummy memory cell.
13. The method of claim 10 , comprising:
during the first time interval, applying a pass voltage level to the second dummy memory cell; and
during the second and third time intervals, keeping the pass voltage level on the second dummy memory cell.
14. The method of claim 10 , comprising:
during the first time interval, applying a blocking voltage lower than the first voltage level to the selected word line.
15. The method of claim 10 , comprising:
during the first time interval, applying a blocking voltage to unselected word lines corresponding to unselected memory cells in the plurality of memory cells;
during the second time interval, applying a pass voltage to the unselected word lines and the selected word line, the pass voltage being lower than the program voltage; and
during the third time interval, keeping the pass voltage on the unselected word lines.
16. The method of claim 10 , the memory device including a third dummy memory cell arranged in series between the first and second dummy memory cells, the method comprising:
during the first time interval, applying a pass voltage level to the third dummy memory cell; and
during the second and third time intervals, keeping the pass voltage level on the third dummy memory cell.