Method for fabricating array substrate, array substrate and display device
The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may comprise: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound. By converting only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the metal thin film layer, such as a low-resistance metal (e.g., Cu or Ti) layer, in the subsequent procedures, which is favorable for the fabrication of a metal oxide thin film transistor using Cu or Ti.
1. A method for fabricating an array substrate, comprising:
forming a metal thin film pattern including a source electrode, a drain electrode and a data line;
forming a non-crystalline semiconductor thin film layer on the metal thin film pattern; and
performing annealing to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound and obtain a source metal semiconductor compound layer, a drain metal semiconductor compound layer and a metal semiconductor compound layer for the data line, such that each of the source electrode, the drain electrode and the data line is a double-layer structure, the double-layer structure comprising a lower metal thin film layer and a corresponding upper metal semiconductor compound layer,
wherein the method further comprises removing the non-crystalline semiconductor thin film layer outside the regions of the source electrode, drain electrode and data line,
wherein the non-crystalline semiconductor thin film layer comprises a layer of α-silicon, α-germanium, α-gallium arsenide, α-arsenic sulfide or α-selenium,
wherein the metal semiconductor compound comprises a silicide of titanium, a germanide of titanium, a compound of titanium and α-gallium arsenide, a compound of titanium and α-arsenic sulfide, or a compound of titanium and α-selenium,
wherein a temperature for the annealing ranges between 200° C. and 280° C.
2. The method according to claim 1 , further comprising:
prior to forming the metal thin film pattern including the source electrode, drain electrode and data line, forming on the substrate a gate, a gate line, a gate insulation layer covering the gate and the gate line, and an active layer arranged on the gate insulation layer and corresponding to the gate.
3. The method according to claim 2 , wherein the step of forming a metal thin film pattern including a source electrode, a drain electrode and a data line comprises:
forming a metal thin film layer; and
removing the metal thin film layer outside regions of the source electrode, drain electrode and data line through a patterning process.
4. The method according to claim 3 , wherein the metal thin film layer comprises a layer of copper or titanium.
5. The method according to claim 2 , wherein the active layer is a metal oxide layer.
6. The method according to claim 5 , wherein the metal oxide layer comprises an indium gallium zinc oxide, indium tin zinc oxide or nitrogen-doped zinc oxide semiconductor layer.
7. The method according to claim 1 , further comprising:
forming a passivation layer, and etching portions of the passivation layer corresponding to the drain electrode, gate line and data line to form corresponding through-holes.
8. The method according to claim 7 , further comprising:
forming a via-hole in the gate insulation layer at a position corresponding to the gate line on the gate insulation layer.
9. The method according to claim 8 , further comprising:
forming a transparent conductive thin film and forming a pattern including a pixel electrode, a connection line for the gate line and a connection line for the data line on the passivation layer with the through-holes through a patterning process, wherein the drain metal semiconductor compound layer is electrically connected to the pixel electrode by means of the through-hole corresponding to the drain electrode.
10. The method according to claim 8 , wherein the metal thin film layer comprises a layer of copper or titanium.
11. The method according to claim 7 , wherein the metal thin film layer comprises a layer of copper or titanium.
12. The method according to claim 1 , wherein the metal thin film layer comprises a layer of copper or titanium.
13. The method according to claim 1 , wherein the thickness of the non-crystalline semiconductor thin film layer is 10 Å-50 Å.
14. The method according to claim 1 , wherein the annealing is performed under nitrogen atmosphere.