Formation of self-aligned bottom spacer for vertical transistors

1. A method of fabricating a semiconductor device, the method comprising:

forming a fin on a substrate;

forming source/drain regions arranged on the substrate on opposing sides of the fin;

depositing a semiconductor layer on the source/drain regions;

depositing a germanium containing layer on the fin and the semiconductor layer; and

applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

2. The method of claim 1 , wherein the semiconductor layer comprises silicon germanium.

3. The method of claim 2 , wherein, subsequent to annealing, the silicon oxide layer is arranged on a silicon germanium layer that includes a higher content of germanium than the semiconductor layer.

4. The method of claim 2 , wherein the silicon germanium comprises from about 20 to about 60 atomic percentage (%) germanium.

5. The method of claim 3 , wherein the silicon germanium layer that includes a higher content of germanium comprises from about 40 to about 80 atomic % germanium.

6. The method of claim 1 , wherein the germanium containing layer comprises germanium oxide.

7. A method of forming a semiconductor device, the method comprising:

forming a fin on a substrate;

forming source/drain regions arranged on the substrate on opposing sides of the fin;

depositing a first silicon germanium layer on the source/drain regions;

depositing a germanium containing layer on the fin and the first silicon germanium layer;

annealing to chemically react the first silicon germanium layer with the germanium containing layer and form a silicon oxide layer arranged on a second silicon germanium layer with an increased germanium content than the first silicon germanium layer; and

performing a nitridation process to increase a nitrogen content of the silicon oxide layer and form a bottom spacer.

8. The method of claim 7 , wherein the nitridation process comprises rapid thermal nitridation or plasma nitridation.

9. The method of claim 7 , wherein the germanium containing layer comprises GeO 2 .

10. The method of claim 7 , wherein, subsequent to performing the nitridation process, the bottom spacer comprises SiON.

11. The method of claim 7 , wherein, subsequent to performing the nitridation process, the germanium containing layer on sidewalls of the fin forms GeON.

12. The method of claim 11 , further comprising removing the GeON and forming a metal gate on the bottom spacer.

13. A method of fabricating a semiconductor device, the method comprising:

depositing a first silicon germanium layer on a source/drain region arranged on a substrate,

depositing a germanium oxide layer on the fin and the first silicon germanium layer; and

chemically reacting the first silicon germanium layer with the germanium oxide layer to form a silicon oxide layer arranged on a second silicon germanium layer with an increased germanium content than the first silicon germanium layer.

14. The method of claim 13 , wherein the second silicon germanium layer comprises from about 20 to about 30 atomic % more germanium than the first silicon germanium layer.

15. The method of claim 13 further comprising performing a nitridation process to increase a nitrogen content of the silicon oxide layer.

16. The method of claim 15 , wherein the nitridation process is performed at a temperature of from about 600 to about 800° C.

17. The method of claim 13 , wherein the nitridation process forms a SiON layer on the second silicon germanium layer.

18. The method of claim 13 , wherein the silicon oxide layer comprises substantially pure SiO 2 .