Stacked nanosheet field effect transistor floating-gate EEPROM cell and array
Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor located on top of a substrate and connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
1. A semiconductor device, comprising:
a substrate;
a first nanosheet transistor located on top of the substrate and connected to a first terminal;
a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; and
an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
2. The semiconductor device of claim 1 , wherein the first nanosheet transistor is an n-type nanosheet transistor and the second nanosheet transistor is a p-type nanosheet transistor.
3. The semiconductor device of claim 2 , wherein hot-carrier injection is triggered when a voltage across one of the n-type nanosheet transistor and the p-type nanosheet transistor is about 3.0 volts.
4. The semiconductor device of claim 1 , wherein the first nanosheet transistor includes a first low injection-barrier material gate dielectric and the second nanosheet transistor includes a second low injection-barrier material gate dielectric.
5. The semiconductor device of claim 4 , wherein the first low injection-barrier material gate dielectric and the second low injection-barrier material gate dielectric are each selected from a group consisting of silicon nitride (Si 3 N 4 ), yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), and hafnium dioxide (HfO 2 ).
6. The semiconductor device of claim 1 , wherein a voltage of the common floating gate determines a logical state of the semiconductor device.
7. The semiconductor device of claim 1 , wherein the first and second nanosheet transistors are located within a memory cell of an N by M array of memory cells.
8. A memory array, comprising:
an N by M array of memory cells, wherein N represents the number of rows and M represents the number of columns, located on top of a substrate, each memory cell comprising:
a first nanosheet transistor located on top of the substrate and connected to a first terminal;
a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; and
N access transistors, located on top of the substrate and with one of the N access transistors located in each row of the array, wherein each access transistor is connected in series to a low voltage terminal and the common output terminals of M memory cells in a row, and wherein the access transistors are configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
9. The memory array of claim 8 , wherein the first nanosheet transistor is an n-type nanosheet transistor and the second nanosheet transistor is a p-type nanosheet transistor.
10. The memory array of claim 9 , wherein hot-carrier injection is triggered when a voltage across one of the n-type nanosheet transistor and the p-type nanosheet transistor is about 3.0 volts.
11. The memory array of claim 8 , further comprising M bitline terminals connected to the first terminals of the memory cells in respective columns of memory cells.
12. The memory array of claim 11 , further comprising M bitline terminals connected to the second terminals of the memory cells in respective columns of memory cells.
13. The memory array of claim 8 , wherein a voltage of the common floating gate determines a logical state of the semiconductor device.
14. The memory array of claim 8 , wherein the first nanosheet transistor includes a first low injection-barrier material gate dielectric and the second nanosheet transistor includes a second low injection-barrier material gate dielectric.
15. The memory array of claim 8 , further comprising N access wordline terminals connected to gates of the N access transistors.
16. A method of forming a memory cell in a memory array formed from an N by M array of memory cells, the method comprising:
connecting a first nanosheet transistor located on top of a substrate to a first terminal;
connecting a second nanosheet transistor located on top of the first nanosheet transistor, connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; and
connecting an access transistor in series to the common output terminal and to a low voltage terminal, wherein the access transistor is configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.
17. The method of claim 16 , wherein the first nanosheet transistor is an n-type transistor and the second nanosheet transistor is a p-type transistor.
18. The method of claim 17 , wherein the access transistor is configured to trigger hot carrier injection upon application of a voltage across the n-type nanosheet transistor of about 3.0 volts to change a charge on the common floating gate and to write a logical “1” to the memory cell.
19. The method of claim 17 , wherein the access transistor is configured to trigger hot carrier injection upon application of a voltage across the p-type nanosheet transistor of about 3.0 volts to change a charge on the common floating gate and to write a logical “0” to the memory cell.
20. The method of claim 16 , wherein the first nanosheet transistor includes a first low injection-barrier material gate dielectric and the second transistor includes a second low injection-barrier material gate dielectric; and wherein the first low injection-barrier material gate dielectric and the second low injection-barrier material gate dielectric are each selected from a group consisting of silicon nitride (Si 3 N 4 ), yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), and hafnium dioxide (HfO 2 ).