IP Library Granted Patent US 10,283,544
Granted Patent B2
US 10,283,544 · App. 15/746,054 · Granted May 7, 2019

Solid-state imaging element and imaging device

Inventors: Yuhi Yorikado (Kanagawa, JP); Atsushi Toda (Kanagawa, JP); Susumu Inoue (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/14627G02B3/00H01L27/14H01L27/146H01L27/14603H01L27/14629H01L31/02327H01L31/022408H01L31/107H04N5/359H04N5/374
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Quick Facts
Patent No.
US 10,283,544
App. No.
15/746,054
Granted
May 7, 2019
Kind
B2
Abstract

To improve detection efficiency in a solid-state imaging element including a SPAD in which an electrode and wiring are placed in a central portion. A solid-state imaging element includes a photodiode and a light collecting section. The photodiode includes a light receiving surface and an electrode placed on the light receiving surface, and that outputs an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode. The light collecting section causes light from a subject to be collected in the light receiving surface other than a region where the electrode is placed.

Claims (18)

1. A solid-state imaging element comprising:

a photodiode that includes a light receiving surface and an electrode placed on the light receiving surface, and that outputs an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode; and

a light collecting section that causes light from a subject to be collected in the light receiving surface other than a region where the electrode is placed.

2. The solid-state imaging element according to claim 1 , wherein, in the photodiode, the electrode is placed substantially at a center of the light receiving surface.

3. The solid-state imaging element according to claim 1 , wherein the light collecting section includes a microlens having a concavity in a substantially central portion.

4. The solid-state imaging element according to claim 3 , wherein the microlens has an opening in the concavity.

5. The solid-state imaging element according to claim 3 , further comprising:

wiring that is electrically connected the electrode,

wherein the microlens has a concavity continuing along the wiring.

6. The solid-state imaging element according to claim 5 , wherein the microlens has a cut in a bottom portion of the continuing concavity.

7. The solid-state imaging element according to claim 1 , wherein the light collecting section includes a plurality of microlenses each of which is configured to cause light to be collected in the light receiving surface other than a region where the electrode is placed.

8. The solid-state imaging element according to claim 7 , further comprising:

wiring that is placed between the plurality of microlenses adjacent to each other, and that is electrically connected to the electrode.

9. The solid-state imaging element according to claim 7 , wherein each of the plurality of microlenses has a quadrangular bottom surface.

10. The solid-state imaging element according to claim 1 , wherein the light collecting section includes a first light collecting member and a second light collecting member that are sequentially arranged between the electrode and the subject, the second light collecting member having a larger refractive index than the first light collecting member.

11. An imaging device comprising:

a pixel circuit in which pixels each of which includes a photodiode and a light collecting section are arranged in a two-dimensional array form, the photodiode including a light receiving surface and an electrode placed on the light receiving surface, and outputting an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode, the light collecting section causing light from a subject to be collected in the light receiving surface other than a region where the electrode is placed; and

a processing circuit that processes the output electrical signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2018
From: YORIKADO, YUHI; TODA, ATSUSHI; INOUE, SUSUMU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 045095/0548 →
Priority Claims (1)
JP 2015-236329 · Dec 3, 2015 · national
Continuity (1)
Related Publication 20180211990A1 · Jul 26, 2018
Cited By (1)
US 12,320,696