Sample-and-hold circuit with enhanced noise limit
A sample-and-hold circuit is presented that is current driven at the input and current sensed at the output, using two capacitors—one at the input to the ground and second past a pair of complementary CMOS switches at the output to the ground. These capacitors in connection with an input current drive form a highpass noise transfer function that substantially reduces the 1/f noise of the switches and then rolls the transfer function off, further reducing the noise. The overall noise level is significantly lower as compared to a conventional voltage-driven and voltage-sensed sample-and-hold circuit that has a lowpass transfer function which, after integration, demonstrates a noise limit of kT/C. Depending on the circuit parameters the present sample-and-hold circuit shows an integrated noise improvement of between 5 and 10 dB over kT/C limit.
1. A sample-and-hold circuit with an enhanced noise limit, the sample-and-hold circuit comprising:
a first field effect transistor (FET) having a first source drain (S/D) to accept an analog input signal current (I S ), a second S/D, and a gate to accept a binary level first digital control signal;
second FET having a second S/D connected to the first S/D of the first FET, a first S/D connected to the second S/D of the first FET, and a gate to accept a binary level second digital control signal, complementary to the first digital control signal;
a source resistance (Rs) between the first S/D of the first FET and ground;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first FET, and a second terminal connected to ground; and,
wherein the second S/D of the first FET presents a current-sensed analog output signal (I O ) in response to the first and second digital control signals respectively enabling the first and second FETs at a first time.
2. The sample-and-hold circuit of claim 1 wherein the combination of the first FET, second FET, source resistance, and first capacitor create a lowpass current signal transfer function.
3. The sample-and-hold circuit of claim 2 wherein the lowpass current signal transfer function is represented as follows:
I O /I S =g m /( g m +sC 1 );
where s is a complex frequency=jω;
where j is an imaginary unit;
where ω=2 ·π·frequency;
where C 1 represents the capacitance value of C 1 ; and,
where g m is the transconductance of the first and second FETs.
4. The sample-and-hold circuit of claim 3 wherein the combination of the first FET, second FET, source resistance, and first capacitor create a highpass noise transfer function.
5. The sample-and-hold circuit of claim 4 wherein the highpass noise transfer function is represented as follows:
( I O /I n,gm )= sg m C 1 /( g m +sC 1 ); and,
where I n,gm is a switch noise current source associated with the first and second FETs.
6. The sample-and-hold circuit of claim 5 wherein a combined noise transfer function, derived from the lowpass current transfer function (I O /I S ) and highpass noise transfer function (I O /I n,gm ) is represented as follows:
( I O /I n,gm )·( I O /I S )= sg m C 1 /( g m +sC 1 ) 2 .
7. The sample-and-hold circuit of claim 6 wherein the combination of the first FET, second FET, source resistance, and first capacitor create a flat spectrum flicker (1/f) noise response from the first and second FET corner frequency (f P ) to a sampling frequency (f S ), when 1/R S is at least an order of magnitude less than g m .
8. The sample-and-hold circuit of claim 6 wherein the combination of the first FET, second FET, source resistance, and first capacitor create a flat thermal noise (I(f) noise ) response from the first and second FET corner frequency (f P ) to a sampling frequency (f S ), when 1/R S is at least an order of magnitude less than g m .
9. The sample-and-hold circuit of claim 8 wherein
I 2 ( f ) noise =0.1427· kT·g m ;
where k is the Boltzmann constant; and,
where T is the Kelvin temperature.
10. The sample-and-hold circuit of claim 1 further comprising:
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the first FET and a second terminal connected to ground.
11. The sample-and-hold circuit of claim 10 further comprising:
an output resistance (R O ) between the second S/D of the first FET and ground;
wherein the combination of the first FET, second FET, source resistance, output resistance, first capacitor, and second capacitor create a lowpass current signal transfer function represented as follows:
I O /I S =( g m /R O C 1 C 2 )/[ s 2 +sg m ( C 1 +C 2 )/ C 1 C 2 +g m /R S C 1 C 2 ], where g m ·R O is at least greater than 10;
where s is a complex frequency=jω;
where j is an imaginary unit;
where ω=2 ·π·frequency;
where C 1 represents the capacitance value of C 1 ;
where C 2 represents the capacitance value of C 2 ; and,
where g m is the transconductance of the first and second FETs.
12. A sample-and-hold circuit with an enhanced noise limit, the sample-and-hold circuit comprising:
at least a first field effect transistor (FET) having a first source drain (S/D) to accept an analog input signal current (I S ), a second S/D, and a gate to accept a binary level first digital control signal;
a source resistance (R S ) between the first S/D of the first FET and ground;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first FET and a second terminal connected to ground;
a second capacitor having a first terminal connected to the second S/D of the first FET and a second terminal connected to ground; and,
wherein the second S/D of the first FET presents a current-sensed analog output signal (I O ) in response to the first digital control signal enabling the first FET at a first time.
13. The sample-and-hold circuit of claim 12 further comprising:
an output resistance (R O ) between the second S/D of the first FET and ground;
wherein the combination of the first FET, source resistance, output resistance, first capacitor, and second capacitor create a lowpass current signal transfer function represented as follows:
I O /I S =( g m /R O C 1 C 2 )/[ s 2 +sg m ( C 1 +C 2 )/ C 1 C 2 +g m /R S C 1 C 2 ], when g m ·R O is at least greater than 10;
where s is a complex frequency=jω;
where j is an imaginary unit;
where ω=2 ·n ·frequency;
where C 1 represents the capacitance value of C 1 ;
where C 2 represents the capacitance value of C 2 ; and,
where g m is the transconductance of the first FET.