Voltage sampling switch

1. A voltage sampling circuit, comprising:

a first capacitor having a first terminal and a second terminal;

a first pre-charge circuit coupled to a first voltage supply terminal and to the first terminal of the first capacitor, the first pre-charge circuit configured to receive a first control signal and pre-charge the first capacitor to a first voltage;

a switch circuit comprising:

a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the first capacitor, and a body electrode coupled to the second terminal of the first capacitor; and

a second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the first capacitor, and a second current electrode couple to an output terminal of the voltage sampling circuit.

2. The circuit of claim 1 , further comprising a second pre-charge circuit coupled to a second voltage supply terminal and to the second terminal of the first capacitor, the second pre-charge circuit configured to receive a second control signal and pre-charge the first capacitor to a second voltage, the second control signal a complement signal of the first control signal.

3. The circuit of claim 1 , wherein the switch circuit is configured to receive an input voltage signal at the input terminal, the input voltage signal having a voltage range including a voltage higher than a voltage rating of gate oxide for transistors in the switch circuit.

4. The circuit of claim 1 , further comprising a second capacitor having a first terminal coupled to the output terminal and a second terminal coupled to a second voltage supply terminal.

5. The circuit of claim 1 , wherein the output terminal is coupled to an input terminal of a voltage comparator.

6. The circuit of claim 1 , further comprising a boost select circuit coupled to the first capacitor and coupled to the switch circuit, the boost select circuit comprising:

a third transistor having a first current electrode coupled to the first terminal of the first capacitor and a second current electrode coupled to a control electrode of the second transistor at a boost node; and

a fourth transistor having a first current electrode coupled to a control electrode of the third transistor, a control electrode coupled to the boost node, a second current electrode coupled to the second terminal of the first capacitor, and a body electrode coupled to the second terminal of the first capacitor.

7. The circuit of claim 6 , wherein the switch circuit further comprises:

a fifth transistor having a first current electrode coupled to the second terminal of the first capacitor, a control electrode coupled to the boost node, and a body electrode coupled to the second terminal of the first capacitor; and

a sixth transistor having a first current electrode coupled to a second current electrode of the fifth transistor, a control electrode coupled to the first terminal of the first capacitor, a second current electrode coupled to the input terminal of the voltage sampling circuit, and a body electrode coupled to the second terminal of the first capacitor.

8. The circuit of claim 6 , wherein the first pre-charge circuit comprises:

a fifth transistor having a first current electrode coupled to the first voltage supply terminal, and a control electrode coupled to receive a first control signal;

a sixth transistor having a first current electrode coupled to a second current electrode of the fifth transistor, and a control electrode coupled to the second terminal of the first capacitor; and

a seventh transistor having a first current electrode coupled to a second current electrode of the sixth transistor, a control electrode coupled to the boost node, and a second current electrode coupled to the first terminal of the first capacitor.

9. The circuit of claim 6 , further comprising an output disable circuit coupled to the boost node, the output disable circuit comprises:

a fifth transistor having a first current electrode coupled to the boost node;

a sixth transistor having a first current electrode coupled to a second current electrode of the fifth transistor; and

a seventh transistor having a first current electrode coupled to a second current electrode of the sixth transistor, and a second current electrode coupled to a second voltage supply terminal.

10. A voltage sampling circuit, comprising:

a first capacitor having a first terminal and a second terminal;

a first pre-charge circuit coupled to a first voltage supply terminal and to the first terminal of the first capacitor, the first pre-charge circuit configured to receive a first control signal and pre-charge the first capacitor to a first voltage;

a boost select circuit having a first input coupled to the first terminal of the first capacitor and an output coupled to a boost node;

a switch circuit comprising:

a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the first capacitor, and a body electrode coupled to the second terminal of the first capacitor; and

a second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the first capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.

11. The circuit of claim 10 , wherein the switch circuit further comprises:

a third transistor having a first current electrode coupled to the second terminal of the first capacitor, a control electrode coupled to the boost node, and a body electrode coupled to the second terminal of the first capacitor; and

a fourth transistor having a first current electrode coupled to a second current electrode of the fifth transistor, a control electrode coupled to the first terminal of the first capacitor, a second current electrode coupled to the input terminal of the voltage sampling circuit, and a body electrode coupled to the second terminal of the first capacitor.

12. The circuit of claim 10 , further comprising a second pre-charge circuit coupled to a second voltage supply terminal and to the second terminal of the first capacitor, the second pre-charge circuit configured to receive a second control signal and pre-charge the first capacitor to a second voltage.

13. The circuit of claim 10 , further comprising an output disable circuit coupled to the boost node, the output disable circuit comprises:

a third transistor having a first current electrode coupled to the boost node;

a fourth transistor having a first current electrode coupled to a second current electrode of the third transistor; and

a fifth transistor having a first current electrode coupled to a second current electrode of the fourth transistor, and a second current electrode coupled to a second voltage supply terminal.

14. The circuit of claim 10 , wherein the boost select circuit comprises:

a third transistor having a first current electrode coupled to the first terminal of the first capacitor and a second current electrode coupled to a control electrode of the second transistor at the boost node; and

a fourth transistor having a first current electrode coupled to a control electrode of the third transistor, a control electrode coupled to the boost node, a second current electrode coupled to the second terminal of the first capacitor, and a body electrode coupled to the second terminal of the first capacitor.

15. The circuit of claim 10 , further comprising a second capacitor having a first terminal coupled to the output terminal of the voltage sampling circuit and a second terminal coupled to a second voltage supply terminal.

16. The circuit of claim 10 , wherein the output terminal of the voltage sampling circuit is coupled to a first input of a voltage comparator.

17. The circuit of claim 10 , wherein the first voltage is higher than a voltage applied at the first voltage supply terminal.

18. A method comprising:

providing an input voltage signal to an input terminal of a voltage sampling circuit, the input voltage signal having a voltage range including a voltage higher than a voltage rating of gate oxide for transistors in the voltage sampling circuit;

transferring a sampled voltage to an output terminal of the voltage sampling circuit by way of a switch circuit coupled between the input terminal and the output terminal, the switch circuit comprising:

a first transistor having a first current electrode coupled to the input terminal, a control electrode coupled to a first terminal of a first capacitor, and a body electrode coupled to a second terminal of the first capacitor; and

a second transistor having a first current electrode coupled to a second current electrode of the first transistor, a control electrode coupled to a boost node, a second current electrode coupled to the output terminal, and a body electrode coupled to the second terminal of the first capacitor; and

coupling a boosted voltage at the first terminal of a first capacitor to the boost node by way of a boost select circuit, the boosted voltage higher than the sampled voltage, the boost select circuit comprising:

a third transistor having a first current electrode coupled to the first terminal of the first capacitor and a second current electrode coupled to a control electrode of the second transistor at the boost node; and

a fourth transistor having a first current electrode coupled to a control electrode of the third transistor, a control electrode coupled to the boost node, a second current electrode coupled to the second terminal of the first capacitor, and a body electrode coupled to the second terminal of the first capacitor.

19. The method of claim 18 , wherein transferring the sampled voltage to the output terminal by way of the switch circuit occurs during a first phase of a control signal, and wherein the switch circuit is disabled during a second phase of the control signal.

20. The method of claim 19 , further comprising pre-charging the first capacitor to a supply voltage within the voltage rating of the gate oxide during the second phase of the control signal.