Nested quantum annealing correction
Systems and methods of processing using a quantum processor are described. A method includes obtaining a problem Hamiltonian and defining a nested Hamiltonian with a plurality of logical qubits by embedding a logical K N representing the problem Hamiltonian into a larger K C×N , where N represents a number of the logical qubits and C represents a nesting level defining the amount of hardware resources for the nest Hamiltonian. The method also includes encoding the nested Hamiltonian into the plurality of physical qubits of the quantum processor; and performing a quantum annealing process with the quantum processor after the encoding.
1. A method of processing, with error suppression, using a quantum processor, the method comprising:
obtaining a problem Hamiltonian having a first plurality of logical qubits represented by a logical graph K N , each logical qubit of the first plurality of logical qubits being coupled to another logical qubit of the first plurality of logical qubits;
defining a nested Hamiltonian with a second plurality of logical qubits larger than the first plurality of logical qubits by embedding the logical graph K N into a larger logical graph K C×N , where N represents a number of logical qubits in the second plurality of logical qubits, and where C represents a nesting level defining the amount of hardware resources for the nested Hamiltonian, each logical qubit i (i=1, . . . , N) of the first plurality of logical qubits in the logical graph K N being represented by a corresponding C-tuple of logical qubits (i, c) (c=1, . . . , C) of the second plurality of logical qubits in the logical graph K C×N , each coupling between logical qubits of the first plurality of logical qubits being represented by C 2 couplings between the corresponding C-tuples of logical qubits of the second plurality of logical qubits to thereby provide an effective temperature reduction for the problem Hamiltonian during a quantum annealing process of the nested Hamiltonian;
encoding the nested Hamiltonian into a plurality of physical qubits of the quantum processor;
performing the quantum annealing process with the quantum processor after the encoding, where the effective temperature reduction reduces thermal errors during the quantum annealing process;
further comprising: measuring the plurality of physical qubits; and recovering a logical state of each of the plurality qubits using a decoding procedure;
wherein the encoding further comprises performing a minor embedding process comprising implementing each of the second plurality of logical qubits in the nested Hamiltonian as a ferromagnetically coupled chain having a length of L qubits of the plurality of physical qubits, such that all couplings in the nested Hamiltonian are represented by inter-chain couplings; and
wherein the decoding procedure is performed over both (i) the length (L) chain of each encoded qubit of the second plurality of qubits and (ii) C encoded qubits comprising each C-tuple of the second plurality of logical qubits.
2. The method of claim 1 , wherein a number of physical qubits necessary for the minor embedding of the K C×N is K C,phys =CNL˜C 2 N 2 .
3. The method of claim 1 , wherein the hardware resources comprise at least one of physical qubits, couplers, and local fields.
4. The method of claim 1 , wherein the hardware resources comprise nested couplers {tilde over (J)} (i,c),(j,c′) and local fields {tilde over (h)} (i,c) where
{tilde over (J)} (i,c),(j,c′) =J ij ,∀c,c′,i≠j,
{tilde over (h)} (i,c) =Ch i ,∀c,i,
{tilde over (J)} (i,c),(i,c′) =−γ,∀c≠c′.
5. A quantum processing system with error suppression, comprising:
a digital computer comprising a digital processor and a memory having stored thereon instructions for causing the digital processor to:
obtain a problem Hamiltonian having a first plurality of logical qubits represented by a logical graph K N , each logical qubit of the first plurality of logical qubits being coupled to another logical qubit of the first plurality of logical qubits;
define a nested Hamiltonian with a second plurality of logical qubits larger than the first plurality of logical qubits by embedding the logical graph K N into a larger logical graph K C×N , where N represents a number of logical qubits in the second plurality of logical qubits, and where C represents a nesting level defining the amount of hardware resources for the nested Hamiltonian, each logical qubit i (i=1, . . . , N) of the first plurality of logical qubits in the logical graph K N being represented by a corresponding C-tuple of logical qubits (i, c) (c=1, . . . , C) of the second plurality of logical qubits in the logical graph K C×N , each coupling between logical qubits of the first plurality of logical qubits being represented by C 2 couplings between the corresponding C-tuples of logical qubits of the second plurality of logical qubits to thereby provide an effective temperature reduction for the problem Hamiltonian during a quantum annealing process of the nested Hamiltonian;
an analog computer coupled to the digital computer, the analog computer comprising a quantum processor and configured for:
encoding the nested Hamiltonian into a plurality of physical qubits of the quantum processor, and
performing the quantum annealing process with the quantum processor after the encoding, where the effective temperature reduction reduces thermal errors during the quantum annealing process;
wherein the analog computer is configured for measuring the plurality of physical qubits, and wherein the instructions further comprise instructions for causing the digital processor to recover a logical state of each of the plurality qubits using a decoding procedure;
wherein the encoding further comprises performing a minor embedding process comprising implementing each of the second plurality of logical qubits in the nested Hamiltonian as a ferromagnetically coupled chain having a length of L qubits of the plurality of physical qubits, such that all couplings in the nested Hamiltonian are represented by inter-chain couplings; and
wherein the decoding procedure is performed over both (i) the length (L) chain of each encoded qubit of the second plurality of qubits and (ii) C encoded qubits comprising each C-tuple of the second plurality of logical qubits.
6. The method of claim 5 , wherein a number of physical qubits necessary for the minor embedding of the K C×N is K C,phys =CNL˜C 2 N 2 .
7. The system of claim 5 , wherein the hardware resources comprise at least one of physical qubits, couplers, and local fields.
8. The system of claim 5 , wherein the hardware resources comprise nested couplers {tilde over (J)} (i,c),(j,c′) and local fields {tilde over (h)} (i,c) where
{tilde over (J)} (i,c),(j,c′) =J ij ,∀c,c′,i≠j,
{tilde over (h)} (i,c) =Ch i ,∀c,i,
{tilde over (J)} (i,c),(i,c′) =−γ,∀c≠c′.