Lightweight, low overhead debug bus
According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.
1. An apparatus comprising:
an interconnect bus configured to connect to combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock;
an interconnect-to-debug bus interface configured to translate communications between the interconnect bus and a debug bus;
the debug bus comprising a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock; and
wherein each of the plurality of debug wrapper circuits is configured to:
identify if the respective debug wrapper circuit is activated by the debug bus,
receive a non-invasive input from a respective combinatorial logic block, and
place the non-invasive input from the respective combinatorial logic block on the debug bus.
2. The apparatus of claim 1 , wherein each of the debug wrapper circuits comprises:
a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals.
3. The apparatus of claim 1 , wherein each of the debug wrapper circuits comprises:
a comparator configured to determine, based upon an fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and
a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus.
4. The apparatus of claim 1 , wherein the debug bus is configured to transmit a debug wrapper circuit address on a first clock cycle, and transmit data on a second clock cycle.
5. The apparatus of claim 1 , wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus.
6. The apparatus of claim 1 , wherein each of the debug wrapper circuits comprises a synchronous circuit, operating at the core clock, and configured to separate the plurality of debug wrapper circuits from each other.
7. The apparatus of claim 1 , wherein each of the debug wrapper circuits is configured to only be activated if the interconnect bus is placed in a first transfer mode, wherein the first transfer mode is also employed for non-debug communication.
8. A method comprising:
transmitting a debug command via an interconnect bus configured to connect to combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock;
translating the debug command between the interconnect bus and a debug bus, wherein the debug bus comprises a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication and that operate synchronous to the core clock;
in response to the debug command, placing data from a selected debug wrapper circuit on the debug bus; and
returning the data via the interconnect bus.
9. The method of claim 8 , wherein each of the plurality of debug wrapper circuits is configured to:
identify if the respective debug wrapper circuit is activated by the debug bus,
receive a non-invasive input from a respective combinatorial logic block, and
place the non-invasive input from the respective combinatorial logic block on the debug bus.
10. The method of claim 9 , wherein each of the debug wrapper circuits comprises:
a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals.
11. The method of claim 8 , wherein each of the debug wrapper circuits comprises:
a comparator configured to determine, based upon an fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and
a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus.
12. The method of claim 8 , wherein placing data from a selected debug wrapper circuit on the debug bus comprises:
transmitting a debug wrapper circuit address on a first clock cycle, and
transmitting data on a second clock cycle.
13. The method of claim 8 , wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus.
14. The method of claim 8 , translating the debug command between the interconnect bus and a debug bus comprises:
activating the debug bus only if the interconnect bus is placed in a first transfer mode, and
wherein the first transfer mode is also employed for non-debug communication.
15. A system comprising:
a graphic processing circuit configured to operate synchronous to a core clock, and manipulate and alter data in a memory to create images for output to a display device;
an interconnect bus configured to connect to combinatorial logical blocks during normal operation of the graphic processing circuit and operate synchronous to the core clock;
an interconnect-to-debug bus interface configured to translate communications between the interconnect bus and a debug bus;
the debug bus comprising a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock; and
wherein each of the plurality of debug wrapper circuits is configured to:
identify if the respective debug wrapper circuit is activated by the debug bus,
receive a non-invasive input from a respective combinatorial logic block, and
place the non-invasive input from the respective combinatorial logic block on the debug bus.
16. The system of claim 15 , wherein each of the debug wrapper circuits comprises:
a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals.
17. The system of claim 15 , wherein each of the debug wrapper circuits comprises:
a comparator configured to determine, based upon a fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and
a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus.
18. The system of claim 15 , wherein the debug bus is configured to transmit a debug wrapper circuit address on a first clock cycle, and transmit data on a second clock cycle.
19. The system of claim 15 , wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus.
20. The system of claim 15 , wherein each of the debug wrapper circuits is configured to only be activated if the interconnect bus is placed in a first transfer mode, wherein the first transfer mode is also employed for non-debug communication.