RFID integrated circuits with antenna contacts on multiple surfaces
Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. A substrate of the RFID IC, or a portion of the IC substrate, electrically couples the first circuit block to at least one of the first and second antenna contacts. The IC includes one or more interfaces or barrier regions that at least partially electrically isolate the first circuit block from the rest of the IC substrate.
1. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
an electrically conductive IC substrate having one of an n-type doping and a p-type doping;
a circuit region within the IC substrate;
an electrically conductive barrier region formed within the IC substrate and having the other one of the n-type doping and the p-type doping, wherein the barrier region electrically isolates the circuit region from the IC substrate;
a first circuit block disposed in the circuit region;
a first antenna contact disposed on a first surface of the IC substrate and electrically coupled to the first circuit block; and
a second antenna, contact disposed on a second surface of the IC substrate opposite the first surface, wherein the electrically conductive IC substrate electrically couples the second antenna contact to the first circuit block.
2. The IC of claim 1 , wherein the first circuit block is:
electrically coupled to the first antenna contact via a first coupling capacitor; and
electrically coupled to the second antenna contact via a second coupling capacitor.
3. The IC of claim 1 , wherein a reverse-biased PN junction between the barrier region and the circuit region provides the electrical isolation.
4. The IC of claim 3 , further comprising a second circuit block electrically coupled to the barrier region and configured to generate a voltage to reverse-bias the PN junction.
5. The IC of claim 1 , wherein:
the IC substrate includes an epitaxial layer and a base layer, wherein the epitaxial layer is disposed above the base layer, and
the circuit region is formed within the epitaxial layer.
6. The IC of claim 1 , wherein at least one of the first and second antenna contacts includes at least one conductive pad spanning substantially an entire surface of the IC substrate.
7. The IC of claim 1 , wherein the first circuit block includes a charge pump electrically coupled to the first and second antenna contacts such that a current flow is from the first antenna contact to the second antenna contact through the electrically conductive IC substrate during a first phase of an incident RF signal and is from the second antenna contact to the first antenna contact through the electrically conductive IC substrate during a second phase of the incident RF signal.
8. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
an electrically conductive IC substrate;
a circuit region formed within the IC substrate and electrically isolated from the substrate;
a first circuit block disposed in the circuit region;
a first antenna contact disposed on a first surface of the IC substrate and electrically coupled to the first circuit block; and
a second antenna contact disposed on a second surface of the IC substrate different from the first surface, wherein the electrically conductive IC substrate electrically couples the second antenna contact to the first circuit block.
9. The IC of claim 8 , wherein the first circuit block is:
electrically coupled to the first antenna contact via a first coupling capacitor; and
electrically coupled to the second antenna contact via a second coupling capacitor.
10. The IC of claim 8 , further comprising an electrically conductive barrier region formed within the IC substrate and separating the circuit region from the IC substrate, wherein:
the barrier region is one of an n-well and a p-well; and
the IC substrate has a doping opposite that of the barrier region.
11. The IC of claim 10 , wherein a reverse-biased PN junction between the barrier region and the circuit region provides the electrical isolation.
12. The IC of claim 11 , further comprising a second circuit block electrically coupled to the barrier region and configured to generate a voltage to reverse-bias the PN junction.
13. The IC of claim 10 , wherein:
the IC substrate includes an epitaxial layer and a base layer, wherein the epitaxial layer is disposed above the base layer; and
the circuit region is formed within the epitaxial layer.
14. A Radio Frequency Identification (RFD) integrated circuit (IC) comprising:
an electrically conductive IC substrate formed of a first type of semiconductor material;
a circuit region within the IC substrate and formed of the first type of semiconductor material;
an electrically conductive barrier region formed within the IC substrate of a second type of semiconductor material different than the first type, wherein the barrier region electrically isolates the circuit region from the IC substrate;
a first circuit block disposed in the circuit region;
a first antenna contact disposed on a first surface of the IC substrate and electrically coupled to the first circuit block; and
a second antenna contact disposed on a second surface of the IC substrate opposite the first surface, wherein the electrically conductive IC substrate electrically couples the second antenna contact to the first circuit block.
15. The IC of claim 14 , wherein the first circuit block is:
electrically coupled to the first antenna contact via a first coupling capacitor; and
electrically coupled to the second antenna contact via a second coupling capacitor.
16. The IC of claim 14 , wherein the first type is p-type semiconductor material and the second type is n-type semiconductor material.
17. The IC of claim 14 , further comprising an interface between the barrier region and the circuit region that provides the electrically isolation in response to the application of a voltage bias across the interface.
18. The IC of claim 14 , further comprising a second circuit block electrically coupled to the barrier region and configured to generate and apply the voltage bias.
19. The IC of claim 14 , wherein:
the IC substrate includes an epitaxial layer and a base layer, wherein the epitaxial layer is disposed above the base layer; and
the circuit region is formed within the epitaxial layer.
20. The IC of claim 14 , wherein at least one of the first and second antenna contacts includes at least one conductive pad spanning substantially an entire surface of the IC substrate.