Scalarization of vector processing

1. A method for processing an instruction sequence of multiple threads for execution in a Single-Instruction-Multiple-Treads (SIMT) computing system, the method comprising:

analyzing, during compile time, the instruction sequence for execution by a processor in the SIMT computing system, wherein the processor includes a scalar unit for scalar execution and a plurality of vector units for vector execution of N threads in parallel;

determining, during the compile time, that a vector processing instruction in the analyzed instruction sequence has (N−M) inactive threads and same source operands for M active threads, wherein N>M≥1; and

generating, during the compile time and in response to the determining, code for the vector processing instruction to be executed by the scalar unit.

2. The method of claim 1 , further comprising:

setting a designated bit in the generated code for the vector processing instruction to indicate the scalar execution.

3. The method of claim 1 , further comprising:

determining that a second instruction in the analyzed instruction sequence has same source operands for the N threads; and

setting a designated bit in the generated code for the second instruction to indicate the scalar execution.

4. The method of claim 1 , further comprising:

replacing the instruction with a scalar instruction to indicate the scalar execution.

5. The method of claim 1 , wherein analyzing the instruction sequence further comprises:

determining whether a basic block in which the instruction is located is a destination of more than one branch; and

determining whether the instruction receives an operand from the more than one branch.

6. The method of claim 1 , further comprising:

detecting, during execution time, that the instruction has been predicted by the compiler for the scalar execution;

dispatching the instruction to the scalar unit; and

broadcasting a result of the scalar execution to destinations of the M active threads.

7. The method of claim 6 , further comprising:

dispatching another instruction to the vector units for execution concurrently with the instruction.

8. A method of executing an instruction sequence of N threads in a Single-Instruction-Multiple-Treads (SIMT) computing system, the method comprising:

detecting, during execution time, that a vector processing instruction in the instruction sequence has (N−K) inactive threads and same source operands for K active threads in a processor of the SIMT computing system, wherein 1≤K≤Threshold<N, and wherein the processor includes a scalar unit for scalar execution and a plurality of vector units for vector execution of the N threads in parallel;

dispatching the vector processing instruction for the scalar execution in response to the detecting; and

executing the vector processing instruction using the scalar unit.

9. The method of claim 8 , wherein detecting the instruction further comprises:

detecting that a designated status register has K bits set as an indication that corresponding K threads are active.

10. The method of claim 9 , further comprising:

sending a result of the scalar execution to destinations of the K active threads.

11. The method of claim 8 , further comprising:

detecting that a designated bit of the vector processing instruction has been set to indicate a compile time predication that the vector processing instruction has the same source operands for the K active threads; and

executing the vector processing instruction by the scalar unit in response to detection of the designated bit being set.

12. The method of claim 8 , further comprising:

dispatching another instruction to the vector units for execution concurrently with the instruction.

13. A Single-Instruction-Multiple-Treads (SIMT) computing system comprising:

a plurality of processors, each of the processors including a scalar unit for scalar execution and a plurality of vector units for vector execution of multiple threads in parallel; and

a scheduler to schedule the multiple threads to each of the processors,

wherein each of the processors is adapted to:

detect, during execution time from code generated by a compiler, that a vector processing instruction of N threads has been determined by a compiler to have (N−M) inactive threads and same source operands for M active threads, wherein N>M≥1; and

execute, in response to determination by the compiler, the vector processing instruction using the scalar unit.

14. The computing system of claim 13 , wherein each of the processors is further adapted to:

detect that a designated bit of the vector processing instruction has been set as an indication of the scalar execution.

15. The computing system of claim 13 , wherein each of the processors further comprises a status register having N bits that correspond to the N threads, and wherein M of the N bit are set as an indication that corresponding M threads are active.

16. The computing system of claim 13 , wherein each of the processors is further adapted to:

detect, during the execution time, that a second instruction which has not been predicted for the scalar execution has one active thread and (N−1) inactive threads; and

execute the second instruction by the scalar unit.

17. The computing system of claim 13 , wherein each of the processors is further adapted to:

detect, during the execution time, that a second instruction which has not been predicted for the scalar execution has (N−K) inactive threads and same source operands for K active threads, wherein 1≤K≤Threshold≤N; and

execute the second instruction by the scalar unit.

18. The computing system of claim 17 , wherein each of the processors is further adapted to:

broadcast a result of the scalar execution to destinations of the K active threads.

19. The computing system of claim 13 , wherein each of the processors is further adapted to:

broadcast a result of the scalar execution to destinations of the M active threads.

20. The computing system of claim 13 , wherein each of the processors is further adapted to:

dispatch another instruction to the vector units for execution concurrently with the instruction.