Memory macro and method of operating the same

1. A memory macro comprising:

a first set of memory cells arranged in columns and rows, the columns of memory cells in the first set of memory cells being arranged in a first direction, the rows of memory cells in the first set of memory cells being arranged in a second direction different from the first direction, each memory cell of the first set of memory cells comprising:

a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage, the first voltage being different from the second voltage;

a second set of memory cells including a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode, the set of retention circuits being responsive to a set of control signals; and

a set of conductive lines being coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells,

wherein the set of retention circuits and the set of conductive lines have one of the following configurations:

the set of retention circuits is arranged in a first column in the first direction, and the set of conductive lines extend in the second direction, or

the set of retention circuits is arranged in a first row in the second direction, and the set of conductive lines extend in the first direction.

2. The memory macro of claim 1 , wherein a retention circuit of the set of retention circuits comprises:

a diode having a first terminal and a second terminal, the second terminal of the diode being coupled to a conductive line of the set of conductive lines; and

a switch having a first terminal, a second terminal and a third terminal, the first terminal of the switch being coupled to the second supply voltage, the second terminal of the switch being configured to receive a control signal of the set of control signals, and the third terminal of the switch being coupled to the first terminal of the diode.

3. The memory macro of claim 2 , wherein the switch comprises:

a p-type transistor having a gate terminal, a drain terminal and a source terminal, the gate terminal of the p-type transistor corresponding to the second terminal of the switch, the drain terminal of the p-type transistor corresponding to the third terminal of the switch, and the source terminal of the p-type transistor corresponding to the first terminal of the switch; or

an n-type transistor having a gate terminal, a drain terminal and a source terminal, the gate terminal of the n-type transistor corresponding to the second terminal of the switch, the drain terminal of the n-type transistor corresponding to the first terminal of the switch, and the source terminal of the n-type transistor corresponding to the third terminal of the switch.

4. The memory macro of claim 2 , wherein the diode comprises:

a p-type transistor having a first terminal, a second terminal and a third terminal, the first terminal of the p-type transistor being coupled to the second terminal of the p-type transistor and the third terminal of the switch, and the third terminal of the p-type transistor being coupled to the conductive line of the set of conductive lines; or

an n-type transistor having a first terminal, a second terminal and a third terminal, the first terminal of the n-type transistor being coupled to the second terminal of the n-type transistor and the third terminal of the switch, and the third terminal of the n-type transistor being coupled to the conductive line of the set of conductive lines.

5. The memory macro of claim 1 , wherein

a number of retention circuits of the set of retention circuits corresponds to a number of rows in the first set of memory cells, if the set of retention circuits is arranged in the first column in the first direction; or

a number of retention circuits of the set of retention circuits corresponds to a number of columns in the first set of memory cells, if the set of retention circuits is arranged in the first row in the second direction.

6. The memory macro of claim 1 , wherein

a number of retention circuits of the set of retention circuits is adjustable responsive to the set of control signals; or

each retention circuit of the set of retention circuits corresponds to static random access memory (SRAM) cells.

7. The memory macro of claim 1 , wherein

the first set of memory cells corresponds to static random access memory (SRAM) cells; or

the second set of memory cells corresponds to dummy SRAM cells.

8. The memory macro of claim 1 , wherein

each conductive line of the set of conductive lines is coupled to a corresponding row of memory cells of the first set of memory cells by the voltage supply node of each memory cell in the corresponding row of memory cells of the first set of memory cells, if the set of conductive lines extend in the second direction; or

each conductive line of the set of conductive lines is coupled to a corresponding column of memory cells of the first set of memory cells by the voltage supply node of each memory cell in the corresponding column of memory cells of the first set of memory cells, if the set of conductive lines extend in the first direction.

9. A memory macro comprising:

a first set of memory cells arranged in columns and rows, the columns of memory cells in the first set of memory cells being arranged in a first direction, the rows of memory cells in the first set of memory cells being arranged in a second direction different from the first direction, each memory cell of the first set of memory cells being configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage, the first voltage being different from the second voltage;

a second set of memory cells including a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode, the set of retention circuits being responsive to a set of control signals, and being arranged in a first column, the first column being arranged in the first direction and being located along a first edge of the memory macro;

a set of dummy memory cells arranged in a first row in the second direction, and being located along a second edge of the memory macro;

a first set of conductive lines overlapping the first set of memory cells, and being coupled to the set of retention circuits and each memory cell of the first set of memory cells, the first set of conductive lines extending in the second direction; and

a second set of conductive lines overlapping the second set of memory cells, being coupled to the set of retention circuits, and extending in the first direction.

10. The memory macro of claim 9 , further comprising:

a set of terminals located along the first edge of the memory macro, and being coupled to the set of retention circuits, and each terminal of the set of terminals being coupled to a corresponding retention circuit of the set of retention circuits.

11. The memory macro of claim 9 , wherein

the first set of conductive lines comprises:

a first conductive line extending in the second direction, and being coupled to a memory cell of the first set of memory cells;

the second set of conductive lines comprises:

a second conductive line extending in the first direction, being coupled to a retention circuit of the set of retention circuits, and being below the first conductive line; and

the memory macro further comprises:

a via between the first conductive line and the second conductive line, and coupling the first conductive line to the second conductive line.

12. The memory macro of claim 11 , wherein

the first conductive line is in a metal 1 (M 1 ) layer; and

a second conductive line is in a metal 0 (M 0 ) layer.

13. The memory macro of claim 9 , wherein a retention circuit of the set of retention circuits comprises:

a switch having a first terminal, a second terminal and a third terminal, the first terminal of the switch being coupled to the second supply voltage, and the second terminal of the switch being configured to receive a control signal of the set of control signals; and

a diode having a first terminal and a second terminal, the first terminal of the diode being coupled to the third terminal of the switch, and the second terminal of the diode being coupled to a conductive line of the second set of conductive lines.

14. The memory macro of claim 13 , wherein the diode comprises:

a p-type transistor having a first terminal, a second terminal and a third terminal, the first terminal of the p-type transistor being coupled to the second terminal of the p-type transistor and the third terminal of the switch, and the third terminal of the p-type transistor being coupled to the conductive line of the second set of conductive lines; or

an n-type transistor having a first terminal, a second terminal and a third terminal, the first terminal of the n-type transistor being coupled to the second terminal of the n-type transistor and the third terminal of the switch, and the third terminal of the n-type transistor being coupled to the conductive line of the second set of conductive lines.

15. The memory macro of claim 13 , wherein the switch comprises:

a p-type transistor having a gate terminal, a drain terminal and a source terminal, the gate terminal of the p-type transistor corresponding to the second terminal of the switch, the drain terminal of the p-type transistor corresponding to the third terminal of the switch, and the source terminal of the p-type transistor corresponding to the first terminal of the switch; or

an n-type transistor having a gate terminal, a drain terminal and a source terminal, the gate terminal of the n-type transistor corresponding to the second terminal of the switch, the drain terminal of the n-type transistor corresponding to the first terminal of the switch, and the source terminal of the n-type transistor corresponding to the third terminal of the switch.

16. The memory macro of claim 13 , wherein

the switch comprises a first Fin field effect transistor (FinFET) having 2 fins or 4 fins; and

the diode comprises a second FinFET having 1 fin or 2 fins.

17. The memory macro of claim 10 , wherein

each retention circuit of the set of retention circuits does not include logic devices;

the set of control signals are generated outside of the memory macro; or

each retention circuit of the set of retention circuits corresponds to static random access memory (SRAM) cells.

18. A method of operating a memory macro, the method comprising:

changing an operational mode of a first set of memory cells of the memory macro from a first mode to a second mode in response to a first signal, the first signal indicating the operational mode of the first set of memory cells, the changing the operational mode comprises:

turning on or off a retention circuit based on the first signal, the retention circuit being part of a second set of memory cells; and

adjusting a voltage provided to the first set of memory cells,

wherein the retention circuit is coupled to the first set of memory cells by at least a first conductive line or a second conductive line, and at least one of the following configurations:

(a) the first set of memory cells, the second set of memory cells and the retention circuit are arranged in a column of the memory macro; or

(b) the first set of memory cells, the second set of memory cells and the retention circuit are arranged in a row of the memory macro.

19. The method of claim 18 , wherein

turning on or off the retention circuit comprises:

turning on or off a switch based on a transition of the first signal from a first logical level to a second logical level;

turning on or off a diode based on the transition of the first signal from the first logical level to the second logical level; and

providing a voltage of a supply voltage to a voltage supply node of a memory cell of the first set of memory cells by the first conductive line and the second conductive line, and

the switch and the diode are part of the retention circuit.

20. The method of claim 18 , wherein adjusting the voltage provided to the first set of memory cells comprises:

adjusting a first voltage provided, by a first supply voltage, to the first set of memory cells; and

adjusting a second voltage provided, by a second supply voltage, to the first set of memory cells, the first voltage differing from the second voltage.