Cut metal gate process for reducing transistor spacing

1. A method comprising:

providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction;

epitaxially growing semiconductor source/drain (S/D) features over the first and the second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and

performing a first etching process to an area between the first and the second fins, wherein the first etching process removes portions of the first and the second semiconductor S/D features and portions of a dielectric layer disposed therebetween.

2. The method of claim 1 , further comprising, before the performing of the first etching process:

forming gate structures over the substrate and the first and the second fins, wherein the gate structures are oriented lengthwise generally along a second direction perpendicular to the first direction,

wherein the first etching process is tuned to selectively etch the first and the second semiconductor S/D features but not the gate structures.

3. The method of claim 2 , wherein the forming of the gate structures includes:

forming temporary gate structures over the substrate and the first and the second fins;

depositing the dielectric layer over the temporary gate structures and the semiconductor S/D features;

removing the temporary gate structures, resulting in gate trenches in the dielectric layer; and

depositing the gate structures in the gate trenches.

4. The method of claim 3 , wherein the depositing of the gate structures includes forming a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer.

5. The method of claim 4 , wherein the performing of the first etching process results in a trench in the dielectric layer in the area between the first and the second fins, further comprising:

depositing one or more dielectric materials in the trench.

6. The method of claim 5 , further comprising:

etching a contact hole that exposes both the first and the second semiconductor S/D features;

depositing a conductive material in the contact hole; and

performing a chemical mechanical planarization (CMP) process to separate the conductive material into a first portion and a second portion, wherein the first and the second portions are electrically connected to the first and the second semiconductor S/D features, respectively, and are isolated from each other by the one or more dielectric materials.

7. The method of claim 2 , wherein:

the structure further includes a third fin over the substrate and oriented lengthwise generally along the first direction;

the gate structures are also formed over the third fin; and

the first etching process is also performed to an area between the second and the third fins.

8. The method of claim 7 , wherein the performing of the first etching process results in a first trench in the dielectric layer, further comprising:

performing a second etching process to the area between the second and the third fins to form a second trench, wherein the second etching process is tuned to selectively etch the gate structures but not the dielectric layer.

9. The method of claim 1 , wherein the first and the second semiconductor S/D features include p-type doped silicon germanium.

10. The method of claim 8 , further comprising:

depositing one or more dielectric materials in the second trench.

11. A method comprising:

providing a structure having:

a substrate;

a first fin, a second fin, and a third fin over the substrate and oriented lengthwise generally along a first direction;

metal gate structures over the first, the second, and the third fins and oriented lengthwise generally along a second direction perpendicular to the first direction, wherein each gate structure includes a high-k dielectric layer and a metal gate electrode;

first and second epitaxial semiconductor source/drain (S/D) features over the first and the second fins respectively, wherein the first and the second epitaxial semiconductor S/D features merge along the second direction; and

a first dielectric layer over the substrate, the first, the second, and the third fins, and the first and the second epitaxial semiconductor S/D features, the first dielectric layer filling space between the metal gate structures;

performing a first etching process to a first area between the first and the second fins and to a second area between the second and the third fins, wherein the first etching process is tuned to selectively etch the first and the second epitaxial semiconductor S/D features and the first dielectric layer but not the metal gate structures;

performing a second etching process to the second area, wherein the second etching process is tuned to selectively etch the metal gate structures to form a trench in the metal gate structures; and

forming a second dielectric layer in the trench.

12. The method of claim 11 , wherein the first etching process removes portions of the first and the second epitaxial semiconductor S/D features and portions of the first dielectric layer disposed therebetween.

13. The method of claim 11 , wherein the trench is a first trench, and wherein the first etching process results in a second trench between the first and the second epitaxial semiconductor S/D features, further comprising:

depositing one or more dielectric materials in the second trench to form a third dielectric layer, wherein the third dielectric layer is separated from the first and the second epitaxial semiconductor S/D features by two continuous interfaces.

14. The method of claim 13 , wherein the first and the second etching processes collectively form a third trench between the second and the third fins, further comprising depositing the one or more dielectric materials in the third trench.

15. The method of claim 11 , wherein the first etching process includes dry etching with an etchant having hydrogen fluoride and ammonia.

16. The method of claim 11 , wherein the second etching process uses a chlorine-containing etchant.

17. A semiconductor structure, comprising:

a substrate;

first and second fins over the substrate and oriented lengthwise generally along a first direction, wherein bottom portions of the first and the second fins are separated by an isolation feature;

first and second epitaxial semiconductor source/drain (S/D) features over the first and second fins, respectively; and

a first dielectric layer disposed between and in physical contact with the first and the second epitaxial semiconductor S/D features, wherein the first dielectric layer is defined by a first interface between the first dielectric layer and the first epitaxial semiconductor S/D feature, and a second interface between the first dielectric layer and the second epitaxial semiconductor S/D feature, and wherein a bottom surface of the first dielectric layer is disposed below a top surface of the isolation feature.

18. The semiconductor structure of claim 17 , further comprising:

gate structures over the first and second fins and oriented lengthwise generally along a second direction perpendicular to the first direction; and

a second dielectric layer over the substrate, the first and second fins, and the first and second epitaxial semiconductor S/D features, the second dielectric layer filling space between the gate structures, wherein the first and the second dielectric layers include different dielectric materials.

19. The semiconductor structure of claim 18 , further comprising a contact etch stop layer between the second dielectric layer and the first and second epitaxial semiconductor S/D features.

20. The semiconductor structure of claim 17 , further comprising:

a first conductive feature over the first epitaxial semiconductor S/D feature; and

a second conductive feature over the second epitaxial semiconductor S/D feature, wherein the first dielectric layer is disposed between the first and the second conductive features.