Bits register for synonyms in a memory system
View Patent ↗A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.
1. An apparatus for tracking and invalidating memory address synonyms in a memory system, the apparatus comprising:
a synonym tracking module configured to establish a bits register for a first virtual address in the memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address;
the synonym tracking module configured to receive a first fetch request to associate a second virtual address with the physical address, the second virtual address being mapped to the physical address to which the first virtual address is mapped, the second virtual address having a second synonym identifier portion;
the synonym tracking module configured to determine a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and
the synonym tracking module configured to register the set of differing bits in the bits register.
2. The apparatus of claim 1 , wherein:
the synonym tracking module is further configured to receive a second fetch request excluding synonyms from mapping to the physical address; and
the synonym tracking module is further configured to generate a set of synonyms within the memory system based on the bits register.
3. The apparatus of claim 2 , wherein the synonym tracking module is further configured to invalidate the set of synonyms within the memory system.
4. The apparatus of claim 2 , wherein the synonym generation module generates the set of synonyms comprises generating each binary combination represented by the bits register.
5. The apparatus of claim 1 , wherein the synonym tracking module is further configured to record the first synonym identifier portion in a first synonym identifier field and a second synonym identifier portion in a second synonym identifier field of a synonym table.
6. The apparatus of claim 5 , wherein the synonym table includes a limited number of synonym identifier fields.
7. The apparatus of claim 6 , wherein the synonym tracking module is further configured to determine that each of the synonym identifier fields of the synonym table contains a respectively corresponding synonym identifier portion.
8. The apparatus of claim 7 , wherein:
responsive to determining that each of the synonym identifier fields of the synonym table contains a respectively corresponding synonym identifier portion, the synonym tracking module being configured to set an overflow bit in the synonym table.
9. The apparatus of claim 6 , wherein the selected number of synonym identifier portions stored directly in the synonym table is less than or equal to four.
10. The apparatus of claim 5 , further comprising:
the synonym tracking module configured to determine a next available synonym identifier field entry in of the synonym table, the next available synonym identifier field not containing a synonym identifier portion; and
the synonym tracking module configured to record a third synonym identifier portion associated with a third virtual address mapped to the physical address in the next available synonym identifier field of the synonym table.