IP Library Granted Patent US 10,325,721
Granted Patent B2
US 10,325,721 · App. 15/082,814 · Granted Jun 18, 2019

Multilayer ceramic electronic device with dielectric layers and internal electrode layers

Inventors: Shogo Murosawa (Tokyo, JP); Toshihiko Kaneko (Tokyo, JP)
Assignee: TDK Corporation
H01G4/012H01G4/1209H01G4/232H01G4/30H01G4/1227
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Quick Facts
Patent No.
US 10,325,721
App. No.
15/082,814
Granted
Jun 18, 2019
Kind
B2
Abstract

A multilayer ceramic electronic device comprising: a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body; a thickness of the dielectric layers is 0.4 μm or less, a width (W0) of the ceramic element body along a width-direction is 0.59 mm or less, a gap (Wgap) between an outer face of the ceramic element body and an end of the internal electrode layers along width-direction of the ceramic element body is 0.010 to 0.025 mm, and a ratio (Wgap/W0) of the gap with respect to the width is 0.025 or more.

Claims (24)

1. A multilayer ceramic electronic device comprising:

a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and

at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body, wherein

a thickness of the dielectric layers is 0.4 μm or less,

a width (W0) of the ceramic element body along a width-direction is 0.59 mm or less,

a gap (Wgap) between an outer face of the ceramic element body and an end of the internal electrode layers along width-direction of the ceramic element body is 0.010 to 0.025 mm,

a ratio (Wgap/W0) of the gap with respect to the width is 0.025 or more, and

Dh/Di≥1.1 is satisfied, in case that

an average grain size of first dielectric grains constituting the dielectric layers placed between the internal electrode layers along a laminating direction is Di, and

an average grain size of third dielectric grains constituting a lead-out area placed between a lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh.

2. The multilayer ceramic electronic device as set forth in claim 1 , wherein a ratio (te/td) of a thickness (te) of the internal electrode layers with respect to a thickness (td) of the dielectric layers is preferably 1.05 or less.

3. A multilayer ceramic electronic device comprising:

a ceramic element body, in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and

at least a pair of external electrodes which are connected to the internal electrode layers on surfaces of the ceramic element body, wherein

a thickness of the dielectric layers is 0.4 μm or less,

a width (W0) of the ceramic element body along a width-direction is 0.59 mm or less,

a gap (Wgap) between an outer face of the ceramic element body and an end of the internal electrode layers along width-direction of the ceramic element body is 0.010 to 0.025 mm, and

a ratio (Wgap/W0) of the gap with respect to the width is 0.025 or more,

Dg/Di≥1 is satisfied, in case that

an average grain size of first dielectric grains constituting the dielectric layer placed between the internal electrode layers along a laminating direction is Di and

an average grain size of second dielectric grains in an exterior area placed outside of the laminating direction of an interior area, in which the internal electrode layers are laminated interposing the dielectric layers along the laminating direction, is Dg, and

Dh/Di≥1.1 is satisfied, in case that

an average grain size of third dielectric grains constituting a lead-out placed between a lead-out parts of the internal electrode layers connected to either one of the external electrodes is Dh.

4. The multilayer ceramic electronic device as set forth in claim 3 , wherein a ratio (te/td) of a thickness (te) of the internal electrode layers with respect to a thickness (td) of the dielectric layers is preferably 1.05 or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: MUROSAWA, SHOGO; KANEKO, TOSHIHIKO
To: TDK CORPORATION
Reel/Frame 038123/0288 →
Priority Claims (1)
JP 2015-067587 · Mar 27, 2015 · national
Continuity (1)
Related Publication 20160284473A1 · Sep 29, 2016