Level shifter circuit generating bipolar clock signals
In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
1. A level shifter circuit comprising:
a first transistor pair coupled at a first input node;
a second transistor pair coupled at a second input node, wherein the first and second transistor pairs couple at a first node, a second node, a third node, and a fourth node;
a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal;
a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and
a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node, wherein the clock generation circuit is configured to generate a first clock at the first node, a second clock at the second node, a third clock at the third node, and a fourth clock at the fourth node.
2. The level shifter circuit of claim 1 , wherein the clock generation circuit is coupled to each of the first, second, third, and fourth nodes via a different capacitor.
3. The level shifter circuit of claim 1 , wherein the first, second, third, and fourth clocks are configured to generate the first and the second bipolar clock signals.
4. The level shifter circuit of claim 1 , wherein the first, second, third, and fourth clocks are configured to oscillate between a first voltage level and a second voltage level.
5. The level shifter circuit of claim 1 , wherein the first transistor pair is configured to alternatively turn-on and turn-off, wherein the second transistor pair is configured to alternatively turn-on and turn-off.
6. The level shifter circuit of claim 1 , wherein the first bipolar clock signal is configured to oscillate between a first voltage level and a second voltage level, wherein the first input signal is between the first voltage level and the second voltage level, wherein the second bipolar clock signal is configured to oscillate between a third voltage level and a fourth voltage level, wherein the second input signal is between the third voltage level and the fourth voltage level.
7. The level shifter circuit of claim 1 , wherein the third transistor pair is configured to alternatively turn-on and turn-off, wherein the fourth transistor pair is configured to alternatively turn-on and turn-off.