IP Library Granted Patent US 10,326,470
Granted Patent B2
US 10,326,470 · App. 15/347,062 · Granted Jun 18, 2019

Converter for converting code-modulated power with conversion code, and controller thereof

Inventors: Shoichi Hara (Tokyo, JP); Atsushi Yamamoto (Kyoto, JP); Taiki Nishimoto (Osaka, JP); Kohei Masuda (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H03M5/145H02J13/0027H03M5/04
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Quick Facts
Patent No.
US 10,326,470
App. No.
15/347,062
Granted
Jun 18, 2019
Kind
B2
Abstract

A converter includes: a terminal that receives code-modulated power that has been generated with a modulation code; and a circuit that intermittently converts the code-modulated power with a conversion code based on the modulation code. The code-modulated power is alternating-current power.

Claims (38)

1. A converter comprising:

a terminal that receives code-modulated power that has been generated with a modulation code, the code-modulated power being alternating-current power; and

a circuit that intermittently converts the code-modulated power with a conversion code based on the modulation code.

2. The converter according to claim 1 ,

wherein the conversion code is generated from a demodulation code corresponding to the modulation code.

3. The converter according to claim 1 ,

wherein the circuit intermittently converts the code-modulated power to repeatedly output pulse power in a cycle equal to a time span per bit of the modulation code.

4. The converter according to claim 3 ,

wherein the circuit

converts, during a part of the cycle, the code-modulated power into the pulse power with a corresponding bit of the conversion code, and

outputs, during another part of the cycle, no power.

5. The converter according to claim 1 ,

wherein the circuit

converts the code-modulated power with a part of bits of the conversion code, and

outputs no power in accordance with another part of bits of the conversion code.

6. The converter according to claim 1 ,

wherein a rate at which bit values of the conversion code match corresponding bit values of the modulation code is larger than 0.5 and is smaller than 1.

7. The converter according to claim 1 ,

wherein the circuit includes switches.

8. The converter according to claim 7 , further comprising:

a control circuit that generates a plurality of control signals for turning on and off the switches,

wherein the circuit intermittently converts the code-modulated power in accordance with the control signals.

9. The converter according to claim 1 ,

wherein the modulation code includes an orthogonal code.

10. A controller comprising:

a processor that generates a first instruction signal for code-modulating first power into code-modulated power with a modulation code, and generates a second instruction signal for intermittently converting the code-modulated power with a first conversion code based on the modulation code, the code-modulated power being alternating-current power; and

a communication circuit that transmits the first instruction signal to a code modulator, and transmits the second instruction signal to a first converter that is connected with the code modulator through a transmission path.

11. The controller according to claim 10 ,

wherein the processor further generates the conversion code from a demodulation code corresponding to the modulation code.

12. The controller according to claim 10 ,

wherein the processor further sets a time span per bit of the conversion code to be shorter than a time span per bit of the modulation code.

13. The controller according to claim 11 ,

wherein the processor further generates the conversion code by changing at least one bit of the demodulation code.

14. The controller according to claim 11 ,

wherein the processor further generates a third instruction signal for intermittently converting the code-modulated power with a second conversion code based on the modulation code, and

the communication circuit further transmits the third instruction signal to a second converter that is connected with the code modulator through the transmission path.

15. The controller according to claim 14 ,

wherein the processor causes the first converter and the second converter to alternately convert the code-modulated power.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2017
From: HARA, SHOICHI; YAMAMOTO, ATSUSHI; NISHIMOTO, TAIKI; MASUDA, KOHEI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 041479/0293 →
Priority Claims (1)
JP 2015-236547 · Dec 3, 2015 · national
Continuity (1)
Related Publication 20170163281A1 · Jun 8, 2017