Input-pattern aware reference generation system and computing-in-memory system including the same

1. An input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines, the plurality of word lines being selectively activated by an input signal such that each of the plurality of bit lines generates a computational result of multiply-and-accumulate (MAC) computation, the system comprising:

an input counting circuit, receiving the input signal of the memory cell array, discovering input activated word lines according to the input signal and generating a number signal representing a number of the input activated word lines;

a reference array, comprising a plurality of reference memory cells storing a predetermined set of weights; and

a reference word line control circuit, electrically connected between the input counting circuit and the reference array, the reference word line control circuit controlling the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array according to the number signal.

2. The system of claim 1 , wherein the reference array comprises a plurality of reference bit lines, and the predetermined set of weights is arranged such that the plurality of reference bit lines each represents a possible MAC computational result of a combination of 0's and 1's stored in each memory cell of the memory cell array.

3. The system of claim 2 , wherein the plurality of reference signals are selected according to outputs of the reference bit lines.

4. The system of claim 3 , wherein the plurality of reference signals each represents an average of two neighboring outputs of the reference bit lines.

5. The system of claim 1 , wherein the reference array comprises one or more reference sub-array and each of the reference sub-arrays comprises m reference word lines crossing n reference bit lines; wherein when the number signal is q, q reference word lines among m reference word lines are activated according to the input signal, the n reference bit lines generate at least q+1 MAC computational results corresponding to combinations of r 1's and s 0's, wherein m, n, and q are integers, 0≤r, s≤q, and r+s=q.

6. The system of claim 1 , wherein the reference signals are voltage signals or current signals.

7. The system of claim 1 , wherein the memory cell array is a non-volatile memory (NVM) used in a computing-in-memory (CIM) application.

8. A system for computing-in-memory approach, comprising:

a memory cell array having a plurality of word lines crossing a plurality of bit lines, the plurality of word lines being selectively activated by an input signal such that each of the plurality of bit lines generates a computational result of multiply-and-accumulate (MAC) computation;

an input-pattern aware reference generation circuit, comprising:

an input counting circuit, receiving the input signal of the memory cell array, and discovering input activated word lines according to the input signal and generating a number signal representing a number of input activated word lines;

a reference array, comprising a plurality of reference memory cells storing a predetermined set of weights; and

a reference word line control circuit, electrically connected between the input counting circuit and the reference array, the reference word line control circuit controlling the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array according to the number signal; and

a multi-level sensing current sense amplifier comprising:

a sense amplifier, electrically connected to the memory cell array;

a reference selecting circuit, electrically connected between the reference array and the sense amplifier, the reference selecting circuit selecting and transmitting at least one of the reference signals to the sense amplifier; and

a sense amplifier output latch, electrically connected between the sense amplifier and the reference selecting circuit, the sense amplifier output latch matching the computational result of the bit lines with the candidates and outputting a matched computational result of the bit lines.

9. The system of claim 8 , wherein the reference array comprise a plurality of reference bit lines, and the predetermined set of weights is arranged such that the plurality of reference bit lines each represents a possible MAC computational result of a combination of 0's and 1's stored in each memory cell of the memory cell array.

10. The system of claim 9 , wherein the plurality of reference signals are selected according to outputs of the reference bit lines.

11. The system of claim 10 , wherein the plurality of reference signals each represents an average of two neighboring outputs of the reference bit lines.

12. The system of claim 8 , wherein the reference array comprises one or more reference sub-array and each of the reference sub-arrays comprises m reference word lines crossing n reference bit lines; wherein when the number signal is q, q reference word lines among m reference word lines are activated according to the input signal, the n reference bit lines generate at least q+1 MAC computational results corresponding to combinations of r 1's and s 0's, wherein m, n, and q are integers, 0≤r, s≤q, and r+s=q.

13. The system of claim 8 , wherein the reference signals are voltage signals or current signals.

14. The system of claim 8 , wherein the memory cell array is a non-volatile memory (NVM).