Techniques for power efficient oversampling successive approximation register

1. A system for a noise-shaping successive approximation register analog-to-digital-converter comprising:

a successive approximation register (SAR) for receiving an analog input signal and outputting a digital decision;

a digital-to-analog converter (DAC) and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle; and

a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, wherein the filter includes a capacitor array having a first plurality of capacitors for filtering the previous analog residue to generate the processed previous analog residue; and

a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output.

2. The system of claim 1 , further comprising a first switch for connecting the capacitor array to the DAC during a sample phase.

3. The system of claim 1 , wherein the filter further comprises an amplifier for amplifying one of the present analog residue and the processed previous analog residue.

4. The system of claim 1 , wherein the filter is one of a finite impulse response filter and an infinite impulse response filter.

5. The system of claim 1 , wherein the filter is a programmable filter and includes a programmable filter order and programmable filter coefficients.

6. A method for noise-shaping in a successive approximation register analog-to-digital converter comprises:

receiving an input analog signal at a successive approximation register (SAR),

converting the input analog signal to a digital signal at the SAR,

switching a DAC to convert the digital signal to a present analog residue for a present conversion cycle,

processing a previous analog residue from a previous conversion cycle at a filter to generate a processed previous analog residue,

outputting the processed previous analog residue to the SAR, and

summing the processed previous analog residue and the present analog residue and generating a summer output.

7. The method of claim 6 , wherein processing the previous analog residue includes:

receiving the previous analog residue at a first capacitor array having a first plurality of capacitors, and

summing charges from the first plurality of capacitors to generate the processed previous analog residue.

8. The method of claim 7 , further comprising

storing the summer output in a second capacitor array having a second plurality of capacitors, and wherein summing includes summing stored charges from the second plurality of capacitors.

9. The method of claim 6 , further comprising amplifying one of the present analog residue and the processed previous analog residue.

10. A system for a successive approximation register analog-to-digital- converter having a noise transfer function comprising:

a successive approximation register (SAR) for receiving an analog input signal and outputting a digital decision;

a first digital-to-analog converter (DAC) and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle;

a second DAC for processing a previous analog residue from a previous conversion cycle, and storing a processed previous analog residue at the end of the previous conversion cycle; and

a filter for receiving the processed previous analog residue from the second DAC and generating a filter output.

11. The system of claim 10 , further comprising a third DAC for processing a third analog residue from a conversion cycle before the previous conversion cycle, and storing a third processed analog residue, wherein the filter is further configured to receive the third processed analog residue from the third DAC.

12. The system of claim 10 , wherein the filter comprises a filter capacitor and an amplifier for amplifying the processed previous analog residue.

13. The system of claim 10 , wherein the filter is configured to a high pass noise transfer function filter.

14. The system of claim 10 , wherein the filter is one of a finite impulse response filter and an infinite impulse response filter.

15. The system of claim 10 , wherein the filter is a programmable filter and includes a programmable filter order and programmable filter coefficients.

16. The system of claim 1 , further comprising

a comparator for comparing the summer output and a first reference signal and generating a comparator output.

17. The system of claim 16 , wherein the filter further comprises an output array having a second plurality of capacitors for receiving the summer output.

18. The system of claim 17 , wherein the summer further sums charges from the second plurality of capacitors in generating a next summer output.

19. The method of claim 6 , further comprising

comparing the summer output and a first reference signal and generating a comparator output.

20. The system of claim 10 , further comprising a comparator for comparing the filter output and the present analog residue, and generating a comparator output.

21. A method for noise-shaping in a successive approximation register analog-to-digital-converter comprising:

receiving an analog input signal at a successive approximation register (SAR);

converting the analog input signal to a digital signal at the SAR;

switching a first digital-to-analog converter (DAC) to convert the digital signal of the SAR to a present analog residue for a present conversion cycle;

processing a previous analog residue from a previous conversion cycle at a second DAC,

storing a processed previous analog residue at the end of the previous conversion cycle, and

receiving, at a filter, the processed previous analog residue from the second DAC, and

generating a filter output.