Vertical vacuum channel transistor with minimized air gap between tip and gate
A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
1. A method for controlling an electric field from a gate structure, the method comprising:
forming a hardmask over a fin stack including a plurality of layers;
forming a first dielectric layer over the hardmask;
forming a sacrificial layer over the first dielectric layer;
etching the sacrificial layer to expose a top surface of the first dielectric layer;
depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer;
removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack; and
forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
2. The method of claim 1 , further comprising forming side spacers adjacent the triangle-shaped epitaxial growths.
3. The method of claim 2 , further comprising depositing a shallow trench isolation (STI) oxide in direct contact with the side spacers.
4. The method of claim 3 , further comprising removing the sacrificial layer to define trenches adjacent the first dielectric layer.
5. The method of claim 4 , further comprising filling the trenches with a conductive material.
6. The method of claim 5 , further comprising recessing the conductive material to form openings.
7. The method of claim 6 , further comprising filling the openings with a nitride-based dielectric.
8. The method of claim 7 , further comprising forming gate, emitter, and collector contacts.
9. A method for controlling an electric field from a gate structure, the method comprising:
forming a first dielectric layer over a hardmask formed over a fin stack including alternating layers of silicon (Si) and silicon germanium (SiGe);
forming a sacrificial layer over the first dielectric layer;
depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer;
removing a SiGe layer of the fin stack to define an air gap within the fin stack; and
forming triangle-shaped epitaxial growths within the air gap defined between two Si layers of the fin stack.
10. The method of claim 9 , further comprising forming side spacers adjacent the triangle-shaped epitaxial growths.
11. The method of claim 10 , further comprising depositing a shallow trench isolation (STI) oxide in direct contact with the side spacers.
12. The method of claim 11 , further comprising removing the sacrificial layer to define trenches adjacent the first dielectric layer.
13. The method of claim 12 , further comprising filling the trenches with a conductive material.
14. The method of claim 13 , further comprising recessing the conductive material to form openings.
15. The method of claim 14 , further comprising filling the openings with a nitride-based dielectric.
16. The method of claim 15 , further comprising forming gate, emitter, and collector contacts.