Gate cut using selective deposition to prevent oxide loss
Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.
1. A method of forming a semiconductor device, comprising:
forming a plurality of gate stacks across a semiconductor fin, each gate stack comprising a gate conductor;
forming an interlayer dielectric between the plurality of gate stacks;
recessing the gate conductor;
forming a protective layer on the interlayer dielectric that leaves the gate stacks exposed after recessing the gate conductor;
etching away the gate conductor of at least one gate stack; and
forming a dielectric liner in a gap left by the etched gate conductor.
2. The method of claim 1 , further comprising forming a self-assembled monolayer on a top surface of each gate stack before forming the protective layer.
3. The method of claim 1 , wherein the protective layer is a layer of hafnium dioxide.
4. The method of claim 3 , wherein the protective layer has a thickness of less than about 2 nm.
5. The method of claim 1 , further comprising removing the protective layer after etching away the gate conductor.
6. The method of claim 1 , wherein forming the gate stack comprises:
forming a gate dielectric layer over the fins;
forming a work function metal layer over the gate dielectric layer that completely covers the gate dielectric layer; and
forming the gate conductor over the work function metal layer.
7. The method of claim 1 , wherein the semiconductor fins are formed on a semiconductor substrate that comprises at least one shallow trench isolation region and wherein the gate conductor that is etched away belongs to a gate stack formed at least partially over a shallow trench isolation region.
8. The method of claim 1 , further comprising forming source and drain regions on respective sides of a gate stack.
9. A method of forming a semiconductor device, comprising:
forming a plurality of gate stacks across a semiconductor fin on a semiconductor substrate, each gate stack comprising a gate conductor, wherein the semiconductor substrate comprises at least one shallow trench isolation region;
forming an interlayer dielectric between the plurality of gate stacks;
forming a self-assembled monolayer on a top surface of each gate stack;
forming a hafnium dioxide layer on the interlayer dielectric, leaving the self-assembled monolayer exposed;
etching away the gate conductor of at least one gate stack over the at least one shallow trench isolation region;
removing the hafnium dioxide layer after etching away the gate conductor; and
forming a dielectric liner in a gap left by the etched gate conductor.
10. The method of claim 9 , further comprising recessing the gate conductor before forming the protective layer.
11. The method of claim 9 , wherein the hafnium dioxide layer has a thickness of less than about 2 nm.
12. The method of claim 9 , wherein forming the gate stack comprises:
forming a gate dielectric layer over the fins;
forming a work function metal layer over the gate dielectric layer that completely covers the gate dielectric layer; and
forming the gate conductor over the work function metal layer.
13. A method of forming a semiconductor device, comprising:
forming a plurality of gate stacks across a semiconductor fin, each gate stack comprising a gate conductor;
forming an interlayer dielectric between the plurality of gate stacks;
forming a self-assembled monolayer on a top surface of each gate stack;
forming a protective layer on the interlayer dielectric that leaves the gate stacks exposed after forming the self-assembled monolayer;
etching away the gate conductor of at least one gate stack; and
forming a dielectric liner in a gap left by the etched gate conductor.
14. The method of claim 13 , further comprising recessing the gate conductor before forming the protective layer.
15. The method of claim 13 , wherein the protective layer is a layer of hafnium dioxide.
16. The method of claim 15 , wherein the protective layer has a thickness of less than about 2 nm.
17. The method of claim 13 , further comprising removing the protective layer after etching away the gate conductor.
18. The method of claim 13 , wherein forming the gate stack comprises:
forming a gate dielectric layer over the fins;
forming a work function metal layer over the gate dielectric layer that completely covers the gate dielectric layer; and
forming the gate conductor over the work function metal layer.
19. The method of claim 13 , wherein the semiconductor fins are formed on a semiconductor substrate that comprises at least one shallow trench isolation region and wherein the gate conductor that is etched away belongs to a gate stack formed at least partially over a shallow trench isolation region.
20. The method of claim 13 , further comprising forming source and drain regions on respective sides of a gate stack.