IP Library Granted Patent US 10,354,967
Granted Patent B2
US 10,354,967 · App. 15/456,882 · Granted Jul 16, 2019

Metal pillar in a film-type semiconductor package

Inventors: Jung-woo Kim (Osan-si, KR); Woon-bae Kim (Seoul, KR); Bo-in Noh (Suwon-si, KR); Go-woon Seong (Hwaseong-si, KR); Ji-yong Park (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L24/13H01L24/05H01L24/08H01L24/81H01L2224/0401H01L2224/05558H01L2224/05573H01L2224/05584H01L2224/13111H01L2224/13144H01L2224/13147H01L2224/13166H01L2224/13611H01L2224/13644H01L2224/13647H01L2224/13655H01L2224/16225H01L2224/16502H01L2224/32225H01L2224/73204H01L2224/81193H01L2224/81805H01L2924/19105
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Quick Facts
Patent No.
US 10,354,967
App. No.
15/456,882
Granted
Jul 16, 2019
Kind
B2
Abstract

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.

Claims (46)

1. A film-type semiconductor package comprising:

a metal lead portion on a film substrate;

a semiconductor chip including a pad; and

a bump connecting the metal lead portion to the pad of the semiconductor chip, the bump including,

a metal pillar on the pad and including a first metal; and

a soldering portion on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal the soldering portion having a top surface that is substantially flat; and

wherein the metal lead portion comprises a metal lead and a lead protective layer protecting a surface of the metal lead, and a lower surface of the metal lead portion is below and within the top surface of the soldering portion;

the metal lead includes a copper layer, and

the lead protective layer includes a tin layer.

2. The film-type semiconductor package of claim 1 , wherein the metal pillar comprises a gold layer or a copper layer.

3. The film-type semiconductor package of claim 1 , wherein the soldering portion comprises a gold-tin eutectic alloy layer.

4. The film-type semiconductor package of claim 3 , wherein a content of tin atoms in the gold-tin eutectic alloy layer is equal to or greater than about 25% and equal to or less than about 45%.

5. The film-type semiconductor package of claim 1 , wherein the soldering portion surrounds a bottom and opposite side surfaces of the metal lead portion.

6. The film-type semiconductor package of claim 1 , wherein a diffusion preventing layer includes a third metal that is different from the first metal and the second metal.

7. The film-type semiconductor package of claim 6 , wherein the diffusion preventing layer comprises a nickel layer.

8. A film-type semiconductor package comprising:

a metal lead portion extending from an outer lead bonding portion at one side portion of a film substrate to an inner lead bonding portion;

a semiconductor chip including a pad; and

a bump connecting the metal lead portion of the inner lead bonding portion to the pad of the semiconductor chip, the bump including,

a metal pillar on the pad and including a first metal; and

a soldering portion on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal the soldering portion having a top surface that is substantially flat; wherein

the metal lead portion includes a metal lead and a lead protective layer protecting a surface of the metal lead, and a lower surface of the metal lead portion is below and within the top surface of the soldering portion;

the metal lead includes a copper layer, and

the lead protective layer includes a tin layer.

9. The film-type semiconductor package of claim 8 , wherein the outer lead bonding portion comprises a connection portion bonded to an image display panel or a printed circuit board.

10. The film-type semiconductor package of claim 8 , wherein:

the metal pillar includes a gold layer or a copper layer, and

the soldering portion includes a gold-tin eutectic alloy layer.

11. The film-type semiconductor package of claim 10 , wherein a content of tin atoms in the gold-tin eutectic alloy layer is equal to or greater than about 25 at % and equal to or less than about 45 at %.

12. The film-type semiconductor package of claim 8 , further comprising:

a diffusion preventing layer on the metal pillar, the diffusion preventing layer including a nickel layer.

13. The film-type semiconductor package of claim 8 , further comprising:

a barrier layer between the pad and the metal pillar.

14. A bonding bump bonded to a lead portion in a semiconductor package, the bonding bump comprising:

a metal pillar including a first metal; and

a soldering portion including a first soldering layer on the metal pillar, the soldering portion being bonded to the lead portion and including a eutectic alloy layer of the first metal including a second metal, the soldering portion having a top surface that is substantially flat; wherein

the lead portion includes a metal lead and a lead protective layer protecting a surface of the metal lead, and a lower surface of the metal lead is below and within the top surface of the soldering portion,

the metal lead includes a copper layer, and

the lead protective layer includes a tin layer.

15. The bonding bump of claim 14 , wherein:

the soldering portion further comprises a second soldering layer; and

a melting point of the first soldering layer is lower than the melting point of the second soldering layer.

16. The bonding bump of claim 14 , wherein:

the first metal includes at least one of gold and copper; and

the second metal includes tin.

17. The semiconductor package of claim 14 , further comprising a diffusion preventing layer between the soldering portion and the pillar, the diffusion preventing layer including a third metal having a higher melting point than at least one of the first metal and the second metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2017
From: KIM, JUNG-WOO; KIM, WOON-BAE; NOH, BO-IN; SEONG, GO-WOON; PARK, JI-YONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 041576/0417 →
Priority Claims (1)
KR 10-2016-0125590 · Sep 29, 2016 · national
Continuity (1)
Related Publication 20180090459A1 · Mar 29, 2018
Cited By (1)
US 12,642,117