Enhanced field bipolar resistive RAM integrated with FDSOI technology

1. A semiconductor structure comprising:

a functional gate structure located on a topmost surface of a fully depleted semiconductor channel material layer;

a faceted drain-side structure located on the topmost surface of the fully depleted semiconductor channel material layer and present on a first side of the functional gate structure;

a faceted source-side structure located on the topmost surface of the fully depleted semiconductor channel material layer and present on a second side of the functional gate structure that is opposite the first side; and

a resistive random access memory stack located on a surface of the faceted drain-side structure.

2. The semiconductor structure of claim 1 , wherein the resistive random access memory stack includes a bottom electrode, a resistive switching layer and a top electrode.

3. The semiconductor structure of claim 2 , wherein the top electrode has a topmost surface that is coplanar with a topmost surface of the resistive switching layer, and the bottom electrode is locate entirely beneath the resistive switching layer.

4. The semiconductor structure of claim 1 , wherein the resistive random access memory stack includes a resistive switching layer and a top electrode, wherein the resistive switching layer is in direct physical contact with the faceted drain-side structure.

5. The semiconductor structure of claim 4 , wherein the top electrode has a topmost surface that is coplanar with a topmost surface of the resistive switching layer, and the bottom electrode is located entirely beneath the resistive switching layer.

6. The semiconductor structure of claim 1 , wherein the faceted drain-side structure has a triangular shape including a base and a tip, wherein the base is located on the topmost surface of the fully depleted semiconductor channel material layer, and the tip directly contacts the resistive random access memory stack.

7. The semiconductor structure of claim 1 , wherein the faceted drain-side structure comprises, from bottom to top, a drain-side doped semiconductor material and a drain-side metal semiconductor alloy.

8. The semiconductor structure of claim 1 , further comprising an interlayer dielectric (ILD) material laterally adjacent the resistive random access memory stack and the functional gate stack.

9. The semiconductor structure of claim 1 , further comprising a drain contact metal located on a surface of a top electrode of the resistive random access memory stack.

10. The semiconductor structure of claim 9 , further comprising a drain-side contact structure contacting the drain contact metal, a source-side contact structure contacting the faceted source-side structure, and a gate contact structure contacting a gate conductor of the functional gate structure.

11. The semiconductor structure of claim 1 , wherein the fully depleted semiconductor channel material layer is located on an insulator layer, and the insulator layer is located on a handle substrate.

12. The semiconductor structure of claim 1 , wherein an isolation structure surrounds the fully depleted semiconductor channel material layer.

13. A method of forming a semiconductor structure, the method comprising:

forming a gate structure on a topmost surface of a fully depleted semiconductor channel material layer;

forming a faceted drain-side structure on the topmost surface of the fully depleted semiconductor channel material layer and on a first side of the gate structure, and a faceted source-side structure on the topmost surface of the fully depleted semiconductor channel material layer and on a second side of the gate structure that is opposite the first side;

forming an interlayer dielectric (ILD) material laterally adjacent the gate stack and atop the faceted drain-side structure, and atop the faceted source-side structure;

forming a contact opening in the ILD material to physically expose a surface of the faceted drain-side structure; and

forming a resistive random access memory stack in the contact opening and on the physically exposed surface of the faceted drain-side structure.

14. The method of claim 13 , wherein the forming the resistive random access memory stack comprises:

forming a bottom electrode layer in the drain-side contact opening and on the physically exposed surface of the faceted drain-side structure;

forming an organic planarization layer (OPL) on the bottom electrode;

removing vertical extending portions of the bottom electrode layer not protected by the OPL;

removing the OPL;

forming a resistive switching layer; and

forming a top electrode on the resistive switching layer.

15. The method of claim 13 , wherein the forming the resistive random access memory stack comprises:

forming a resistive switching layer in the drain-side contact opening and on the physically exposed surface of the faceted drain-side structure; and

forming a top electrode on the resistive switching layer.

16. The method of claim 13 , further comprising forming a drain contact metal on a surface of a top electrode of the resistive random access memory stack.

17. The method of claim 16 , further comprising forming a drain-side contact structure contacting the drain contact metal, a source-side contact structure contacting the faceted source-side structure, and a gate contact structure contacting a gate conductor of the gate structure.

18. The method of claim 13 , wherein the forming of the faceted drain-side structure comprises:

epitaxially growing a faceted and doped drain-side semiconductor material; and

forming a drain-side metal semiconductor alloy in an upper portion of the faceted and doped drain-side semiconductor material.

19. The method of claim 13 , wherein the fully depleted semiconductor channel material layer is located on an insulator layer, and the insulator layer is located on a handle substrate.

20. The method of claim 13 , wherein an isolation structure is formed surrounding the fully depleted semiconductor channel material layer.