Techniques for forming multiple work function nanosheet device
A method of forming a three-dimensional transistor device may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may include directing angled oxygen ions at the CMOS nanosheet device structure. As a result an oxide may be formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, while an oxide is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack. The method may include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.
1. A method of forming a three-dimensional transistor device, comprising:
performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate;
directing angled oxygen ions at the CMOS nanosheet device structure, wherein an oxide is formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, and wherein an oxide layer is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack; and
performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.
2. The method of claim 1 , wherein the vertical etch comprises a reactive ion etching operation, wherein the first work function metal is a TiN layer, wherein the oxide layer comprises titanium dioxide, and wherein the reactive ion etching operation selectively etches the TiN layer with respect to the titanium dioxide.
3. The method of claim 1 , further comprising:
performing a first block patterning operation to expose second polarity regions in the CMOS nanosheet device structure, before the direction the performing the vertical etch.
4. The method of claim 3 , further comprising:
performing a second block patterning operation to protect first polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the first work function metal from the second nanowire stack while not etching the first work function metal from the first nanowire stack.
5. The method of claim 4 , further comprising:
after the removing the first work function metal, performing a second blanket deposition of a second work function metal over the first nanowire stack and the second nanowire stack.
6. The method of claim 1 , wherein the angled oxygen ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate.
7. The method of claim 6 , wherein a value of the non-zero angle of incidence ranges between 10 degrees and 80 degrees.
8. The method of claim 1 , wherein a dose of the angled oxygen ions ranges from 1E16/cm 2 to 2E17/cm 2 .
9. The method of claim 1 , wherein an energy of the angled oxygen ions is 2 keV or less.
10. The method of claim 1 , wherein a thickness of the oxide layer is 1 nm to 4 nm.
11. A method of forming a three-dimensional transistor device, comprising;
performing a first blanket deposition of a P-type work function metal over a P-type nanowire stack and over an N-type nanowire stack, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate;
directing angled oxygen ions at the CMOS nanosheet device structure, wherein an oxide is formed in the P-type work function metal along a top region of the P-type nanowire stack and the N-type nanowire stack, and wherein an oxide is not formed in the P-type work function metal at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack; and
performing a vertical etch to remove the P-type work function metal between the P-type nanowire stack and the N-type nanowire stack, while not removing the P-type work function metal above the P-type nanowire stack and the N-type nanowire stack.
12. The method of claim 11 , wherein the vertical etch comprises a reactive ion etching operation, wherein the P-type work function metal is a TiN layer, wherein the oxide is titanium dioxide, and wherein the reactive ion etching operation selectively etches the TiN layer with respect to the titanium dioxide.
13. The method of claim 11 , further comprising:
performing a first block patterning operation to expose N-type regions in the CMOS nanosheet device structure, before the performing the vertical etch.
14. The method of claim 13 , further comprising:
performing a second block patterning operation to protect P-type polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the P-type work function metal from the N-type nanowire stack while not etching the P-type work function metal from the P-type nanowire stack.
15. The method of claim 11 , wherein the P-type nanowire stack and the N-type nanowire stack comprise a plurality of silicon nanowires, stacked in a vertical configuration, wherein the trench has an aspect ratio of 1 or greater, wherein a trench depth is greater than or equal to a trench width, defining a spacing between the P-type nanowire stack and the N-type nanowire stack.
16. A method of forming a three-dimensional transistor device, comprising;
directing angled oxygen ions at a CMOS nanosheet device structure, comprising a titanium nitride layer disposed over a P-type nanowire stack and over an N-type nanowire stack, wherein titanium oxide is formed in the titanium nitride layer along a top region of the N-type nanowire stack and the P-type nanowire stack, and wherein the titanium oxide is not formed in the titanium nitride layer at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack;
performing a first block patterning operation to expose N-type polarity regions in the CMOS nanosheet device structure; and
performing a vertical etch to selectively remove the titanium nitride layer between the P-type nanowire stack and the N-type nanowire stack, wherein the titanium oxide is not removed along the top region.
17. The method of claim 16 , further comprising:
performing a first block patterning operation to expose the N-type polarity regions in the CMOS nanosheet device structure, before the performing the vertical etch.
18. The method of claim 17 , further comprising:
performing a second block patterning operation to protect P-type regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the titanium nitride layer from the N-type nanowire stack while not etching the titanium nitride layer from the P-type nanowire stack.
19. The method of claim 18 , further comprising:
after the removing the titanium nitride layer, performing a second blanket deposition of an N-type work function metal over the P-type nanowire stack and the N-type nanowire stack.