IP Library › Granted Patent US 10,381,801
Granted Patent B1
US 10,381,801 · App. 15/963,543 · Granted Aug 13, 2019

Device including structure over airgap

Inventor: Di Liang (Santa Barbara, CA)
Assignee: Hewlett Packard Enterprise Development LP
H01S5/18316H01S5/18363H01S5/18369H01S5/18377H01S5/2045H01S5/22H01S5/223H01S5/2206H01S5/3013H01S5/0206H01S5/105H01S5/32H01S5/323
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Quick Facts
Patent No.
US 10,381,801
App. No.
15/963,543
Granted
Aug 13, 2019
Kind
B1
Abstract

A device comprises a substrate, a sacrificial material layer over the substrate, a first solid-state material layer over the sacrificial layer, a dielectric layer over solid-state material layer, and a second solid-state material layer over the dielectric layer. The sacrificial material layer may have an airgap, the solid-state material layer may comprise a structure over the airgap and may be separated from a bulk portion of the first material layer by trenches, where the trenches extend to the airgap.

Claims (30)

1. A device, comprising:

a substrate;

a sacrificial material layer over the substrate, the sacrificial material layer having an airgap;

a first solid-state material layer over the sacrificial layer, the solid-state material layer comprising a structure over the airgap and separated from a bulk portion of the first material layer by trenches, the trenches extending to the airgap;

a dielectric layer over solid-state material layer;

a second solid-state material layer over the dielectric layer.

2. The device of claim 1 , wherein the airgap extends below a portion of the bulk portion of the first solid-state material layer.

3. The device of claim 1 , wherein the structure is a passive photonic device.

4. The device of claim 3 , wherein the structure is a waveguide.

5. The device of claim 4 , wherein the structure is a rib waveguide.

6. The device of claim 1 , wherein the structure, the dielectric, and second solid-state material layer form a capacitor.

7. The device of claim 1 , further comprising a mesa over the second solid-state material layer.

8. The device of claim 7 , wherein the second solid-state material layer has a first crystal structure and mesa comprises a solid-state material having a second crystal structure with a matching lattice with the first crystal structure.

9. The device of claim 8 , wherein the mesa comprises the same solid-state material as the second solid-state material layer and the first crystal structure is the same as the second crystal structure.

10. The device of claim 1 , further comprising an active photonic device over the second solid-state material layer and the airgap.

11. The device of claim 10 , wherein the active photonic device is within a vertical boundary defined by the trenches.

12. The device of claim 1 , further comprising a second dielectric layer over the first dielectric layer.

13. The device of claim 1 , wherein the first material layer comprises an oxide, the first solid-state material layer comprises silicon, and the second solid-state material layer comprises a III-V material.

14. The device of claim 1 , wherein the airgap extends through the entire sacrificial material layer.

15. A method, comprising:

forming trenches extending to a sacrificial material layer in a first solid-state material layer such that the trenches define a structure separated from a bulk portion of the first material layer;

using the trenches to selectively remove a portion of the sacrificial material layer to form an airgap underneath the structure;

disposing a dielectric layer over the first solid-state material layer; and

bonding a wafer comprising a second solid-state material layer to an assembly comprising the sacrificial material layer and the first solid-state material layer.

16. The method of claim 15 , further comprising:

forming a mesa on the second solid-state material layer over the airgap.

17. The method of claim 16 , wherein the mesa comprises the same material as the second solid-state material layer.

18. The method of claim 16 , further comprising coupling a voltage source to a capacitor formed from a portion of the mesa and the structure.

19. The method of claim 15 , wherein disposing the dielectric layer over the first solid-state material layer comprises depositing a first dielectric layer over the first solid-state material layer.

20. The method of claim 19 , further comprising depositing a second dielectric layer on the wafer, and wherein bonding the wafer comprises bonding the second dielectric layer to the first dielectric layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2018
From: LIANG, DI
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 047093/0849 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2018
From: LIANG, DI
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 046065/0565 →
Cited By (2)
US 12,242,142 US 12,645,105