Integrated multiplying successive approximation analog to digital converter

1. An analog-to-digital converter ADC configured to convert an analog input signal into a digital output signal comprising N bits o n , n∈{0, . . . , N−1}, the ADC comprising a controller, a digital-to-analog converter DAC, and a comparator, wherein

the comparator is configured to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC;

the controller is configured to receive the binary signal generated by the comparator and to generate, based on the binary signal, a digital control signal comprising N bits c n , n∈{0, . . . , N−1}; and

the DAC is configured to generate the analog output signal based on the digital control signal generated by the controller;

wherein the controller comprises a register configured to store a previous sum value and an adder configured to determine a test sum value by adding, when the ADC determines a bit o n of the digital output signal, the previous sum value and a test value corresponding to 2 n times a gain factor.

2. The ADC of claim 1 , wherein the test value is represented by a binary representation of the gain factor which is shifted by n bits.

3. The ADC of claim 1 , wherein the controller is configured to generate the digital control signal based on the test sum value, and, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value in the register as a new sum value.

4. The ADC of claim 1 , wherein the ADC is configured to set the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value.

5. The ADC of claim 1 , wherein the ADC is configured to set the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value.

6. The ADC of claim 1 , wherein the controller is configured to start the analog-to-digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value.

7. The ADC of claim 1 , wherein the ADC is configured to start the analog-to-digital conversion by determining the most significant bit MSB o N-1 of the digital output signal first, and continuing, bit by bit, until the least significant bit LSB o 0 of the digital output signal is determined.

8. A controller for controlling operation of an analog-to-digital converter ADC configured to convert an analog input signal into a digital output signal comprising N bits o n , n∈{0, . . . , N−1}, the ADC comprising a digital-to-analog converter DAC and a comparator, wherein the comparator is configured to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC, and the DAC is configured to generate the analog output signal based on a digital control signal, wherein

the controller is configured to receive the binary signal generated by the comparator and to generate, based on the binary signal, the digital control signal comprising N bits c n , n∈{0, . . . , N−1} for controlling the DAC; and

the controller comprises a register configured to store a previous sum value and an adder configured to determine a test sum value by adding, when determining a bit o n of the digital output signal, the previous sum value and a test value corresponding to 2 n times a gain factor.

9. The controller of claim 8 , wherein the test value is represented by a binary representation of the gain factor which is shifted by n bits.

10. The controller of claim 8 , wherein the controller is configured to generate the digital control signal based on the test sum value, and, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value in the register as a new sum value.

11. The controller of claim 8 , wherein the controller is configured to set the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value.

12. The controller of claim 8 , wherein the controller is configured to set the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value.

13. The controller of claim 8 , wherein the controller is configured to start the analog-to-digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value.

14. The controller of claim 8 , wherein the controller is configured to start the analog-to-digital conversion by determining the most significant bit MSB o N-1 of the digital output signal first, and continuing, bit by bit, until the least significant bit LSB o 0 of the digital output signal is determined.

15. A method of converting an analog input signal into a digital output signal comprising N bits o n , n∈{0, . . . , N−1} using a digital-to-analog converter DAC and a comparator, the method comprising:

generating, by the comparator, a binary signal by comparing the analog input signal with an analog output signal of the DAC;

generating, by the DAC, the analog output signal based on a digital control signal comprising N bits c n , n∈{0, . . . , N−1};

generating, based on the binary signal, the digital control signal for controlling the DAC;

storing a previous sum value; and

determining a test sum value by adding, when determining a bit o n of the digital output signal, the previous sum value and a test value corresponding to 2 n times a gain factor.

16. The method of claim 15 , wherein the test value is obtained by shifting a binary representation of the gain factor by n bits.

17. The method of claim 15 , further comprising the steps of:

generating the digital control signal based on the test sum value;

and, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, storing the test sum value as a new sum value.

18. The method of claim 15 , further comprising the step of:

setting the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value.

19. The method of claim 15 , further comprising the step of:

setting the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value.

20. The method of claim 15 , further comprising the step of:

starting the analog-to-digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value.

21. The method of claim 15 , further comprising the steps of:

starting the analog-to-digital conversion by determining the most significant bit MSB o N-1 of the digital output signal first, and continuing, bit by bit, until the least significant bit LSB o 0 of the digital output signal is determined.

22. The method of claim 15 , further comprising the steps of:

determining further o n -values by adding the previous sum value and a further test value corresponding to 2 n times the gain factor, wherein n is an integer which is either smaller than 0 or greater then N−1; and

amending the digital control signal, c m , wherein the new corresponding test sum maps to the {0, . . . , M−1}-range of said digital control signal or setting to maximum that range if exceeded upon finally returning an expanded output signal comprising bits o n , n∈{0, . . . , N−1} based on said determined further test sum value.