Neural network unit with shared activation function units

1. A neural network unit of a processor circuit, comprising:

a first memory that holds rows of N weight words and provides the N weight words of a row to N corresponding neural processing units (NPU);

a second memory that holds rows of N data words and provides the N data words of a row to the N corresponding NPUs;

the N NPUs, each NPU having:

an accumulator; and

an arithmetic unit that performs a series of multiply operations on pairs of the weight words and data words received from the first and second memories to generate a series of products, the arithmetic unit also performs a series of addition operations on the series of products to accumulate an accumulated value in the accumulator;

a plurality of complex activation function units (AFU), each complex AFU is shared by a corresponding plurality of the N NPUs; and

each complex AFU, in a sequential fashion with respect to each NPU of the corresponding plurality of the N NPUs, receives the accumulated value from the NPU and performs a complex activation function on the accumulated value to generate a complex result;

wherein each of the N NPUs also includes a non-shared simple activation function unit that performs a simple activation function on the accumulated value to generate a simple result, the complex activation function units and the simple activation function units are hardware, and the non-shared simple activation function units are less complex and smaller than the complex activation function units.

2. The neural network unit of claim 1 , further comprising:

the activation function normalizes the accumulated value in a non-linear fashion to produce the result that is within a predetermined range of values.

3. The neural network unit of claim 1 , further comprising:

the activation function is at least one of the following list of activation functions: hyperbolic tangent, sigmoid, softplus, and rectify.

4. The neural network unit of claim 1 , further comprising:

each of the plurality of activation function units includes a hardware lookup table for approximating exact values, the activation function is at least one of the following list of activation functions: hyperbolic tangent, sigmoid, and softplus.

5. The neural network unit of claim 4 , further comprising:

each of the hardware lookup tables comprises at least one of the following list of hardware lookup tables: programmable logic array (PLA), read-only memory (ROM), and combinational logic gates.

6. The neural network unit of claim 1 , further comprising:

an N-word buffer that receives from the plurality of AFUs the N results of the activation function on the N accumulated values of the N NPUs; and

the N-word buffer writes the N results to a row of the second memory.

7. The neural network unit of claim 6 , further comprising:

the first memory includes a first address input that specifies a row;

the second memory includes a second address input that specifies a row; and

a sequencer that generates first and second addresses provided to the first and second address inputs, respectively.

8. The neural network unit of claim 7 , further comprising:

the sequencer generates the second address to specify the row of the second memory to which the N-word buffer writes the N results.

9. The neural network unit of claim 8 , further comprising:

the N NPUs are grouped as L groups of J NPUs each; and

for each of J clock cycles, for each group of the L groups:

the sequencer selects one of the J NPUs of the group for provision of its accumulated value to the corresponding one of the L AFUs to perform the activation function on the accumulated value to generate the result.

10. The neural network unit of claim 7 , further comprising:

a memory programmable with instructions executable by the sequencer.

11. The neural network unit of claim 1 , further comprising:

the neural network unit is comprised by a processor having an instruction set and an architectural instruction thereof that instructs the processor to write a plurality of data words from one or more architectural registers of the processor to a location in the second memory specified by the architectural instruction.

12. The neural network unit of claim 1 , further comprising:

the neural network unit is comprised by a processor having an instruction set and an architectural instruction thereof that instructs the processor to write a plurality of weight words from one or more architectural registers of the processor to a location in the first memory specified by the architectural instruction.

13. The neural network unit of claim 1 , further comprising:

the neural network unit is comprised by a processor having an instruction set and an architectural instruction thereof that instructs the processor to read a plurality of data words into one or more architectural registers of the processor from a location in the second memory specified by the architectural instruction.

14. A method, executed in a processor circuit, for operating a neural network unit having first and second memories, N neural processing units (NPU) each having an accumulator and an arithmetic unit, and a plurality of complex activation function units (AFU), each complex AFU is shared by a corresponding plurality of the N NPUs, the method comprising:

providing, by the first memory, a row of N weight words to corresponding ones of the N NPUs;

providing, by the second memory, a row of N data words to the N corresponding NPUs;

performing, by the arithmetic unit, a series of multiply operations on pairs of the weight words and data words received from the first and second memories to generate a series of products;

performing, by the arithmetic unit, a series of addition operations on the series of products to accumulate an accumulated value in the accumulator; and

receiving, by each complex AFU in a sequential fashion with respect to each NPU of the corresponding plurality of the N NPUs, the accumulated value from the NPU and performing a complex activation function on the accumulated value to generate a complex result;

wherein each of the N NPUs also includes a non-shared simple activation function unit that performs a simple activation function on the accumulated value to generate a simple result, the complex activation function units and the simple activation function units are hardware, and the non-shared simple activation function units are less complex and smaller than the complex activation function units.

15. The method of claim 14 , further comprising:

normalizing, by the activation function, the accumulated value in a non-linear fashion to produce the result that is within a predetermined range of values.

16. The method of claim 14 , further comprising:

the activation function is at least one of the following list of activation functions: hyperbolic tangent, sigmoid, softplus, and rectify.

17. The method of claim 14 , further comprising:

receiving, by an N-word buffer, from the plurality of AFUs the N results of the activation function on the N accumulated values of the N NPUs; and

writing, by the N-word buffer, the N results to a row of the second memory.

18. The method of claim 14 , further comprising:

the N NPUs are grouped as L groups of J NPUs each; and

for each of J clock cycles, for each group of the L groups:

selecting one of the J NPUs of the group for provision of its accumulated value to the corresponding one of the L AFUs to perform the activation function on the accumulated value to generate the result.

19. The method of claim 14 , further comprising:

instructing, by an architectural instruction of a processor comprising the neural network unit, the processor to write a plurality of data/weight words from one or more architectural registers of the processor to a location in the second/first memory specified by the architectural instruction.

20. The method of claim 14 , further comprising:

instructing, by an architectural instruction of a processor comprising the neural network unit, the processor to read a plurality of data words into one or more architectural registers of the processor from a location in the second memory specified by the architectural instruction.

21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a neural network unit in a processor circuit, the computer usable program code comprising:

first program code for specifying a first memory that holds rows of N weight words and provides the N weight words of a row to N corresponding neural processing units (NPU);

second program code for specifying a second memory that holds rows of N data words and provides the N data words of a row to the N corresponding NPUs;

the N NPUs, each NPU having:

an accumulator; and

an arithmetic unit that performs a series of multiply operations on pairs of the weight words and data words received from the first and second memories to generate a series of products, the arithmetic unit also performs a series of addition operations on the series of products to accumulate an accumulated value in the accumulator;

third program code for specifying a plurality of complex activation function units (AFU), each complex AFU is shared by a corresponding plurality of the N NPUs; and

each complex AFU, in a sequential fashion with respect to each NPU of the corresponding plurality of the N NPUs, receives the accumulated value from the NPU and performs a complex activation function on the accumulated value to generate a complex result;

wherein each of the N NPUs also includes a non-shared simple activation function unit that performs a simple activation function on the accumulated value to generate a simple result, the complex activation function units and the simple activation function units are hardware, and the non-shared simple activation function units are less complex and smaller than the complex activation function units.