Formation of stacked nanosheet semiconductor devices
A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.
1. A method of fabricating a stacked nanosheet semiconductor device, the method comprising:
forming three-dimensional nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate;
growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer;
partially etching the interlayer dielectric to expose a portion of the first epitaxial layer;
selectively etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer;
etching a portion of the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET;
selectively etching a portion of the first liner and selectively removing a portion of the second epitaxial layer leaving a portion of the first epitaxial layer exposed;
depositing a second insulator layer on the first epitaxial layer, forming an nFET;
wherein the pFET and the nFET are disposed adjacent to one another vertically and wherein a drain of the pFET and a drain of the nFET are electrically connected.
2. The method of claim 1 , wherein forming the nanosheet stacks further comprises patterning a gate structure on the nanosheet stacks and recessing portions of the nanosheet stacks not covered by the gate structure, forming a source and drain on the stacks.
3. The method of claim 2 , wherein forming the nanosheet stacks further comprises forming inner spacers on the silicon germanium layers of the nanosheet stacks and refilling the interlayer dielectric and replacing the gate structure with a gate replacement structure.
4. The method of claim 1 , further comprising depositing a first insulator layer on the pFET and depositing a second insulator layer on the exposed portion of the first epitaxial layer and selectively growing the second epitaxial layer on the second insulator layer.
5. The method of claim 4 , wherein the pFET and the nFET are separated by the second insulator layer.
6. The method of claim 1 , wherein the first epitaxial layer comprises silicon germanium.
7. The method of claim 1 , wherein partially etching the interlayer dielectric is completed with reactive ion etching.
8. The method of claim 1 , wherein the second epitaxial layer comprises silicon epitaxy with in-situ P doping.
9. The method of claim 1 , wherein the first insulator layer and/or the second insulator layer comprise tungsten.
10. The method of claim 1 , wherein a current is transported laterally across the semiconductor device.