Fully aligned via employing selective metal deposition
A method is presented for creating a fully-aligned via (FAV) by employing selective metal deposition. The method includes forming metal lines within a first inter-layer dielectric (ILD) layer, forming a second ILD layer over the first ILD layer, forming a lithographic stack over the second ILD layer to define areas where via growth is prevented, recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack, and performing metal growth over the exposed top surface of the metal lines where via growth is permitted.
1. A method for creating a fully-aligned via (FAV) by employing selective metal deposition, the method comprising:
forming metal lines within a first inter-layer dielectric (ILD) layer;
forming a second ILD layer over the first ILD layer;
forming a lithographic stack over the second ILD layer to define areas where via growth is prevented;
recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack; and
performing metal growth over the exposed top surface of the metal lines where via growth is permitted; and
removing the lithographic stack and depositing a conformal metal nitride cap in direct contact with a top surface and an entire length of sidewalls of the metal growth.
2. The method of claim 1 , further comprising depositing a low-k material layer over the conformal metal nitride cap.
3. The method of claim 2 , further comprising recessing the low-k material layer to expose a top surface of the conformal metal nitride cap over the metal growth.
4. The method of claim 3 , further comprising removing the exposed top surface of the conformal metal nitride cap over the metal growth to expose a top surface of the metal growth.
5. The method of claim 4 , further comprising performing single damascene metallization over the exposed top surface of the metal growth.
6. The method of claim 5 , wherein the metal growth is one or more self-aligned via interconnect structures.
7. The method of claim 6 , wherein, after the recessing of the low-k material layer, portions of the low-k material layer remain between the metal growth and the second ILD layer.
8. The method of claim 1 , further comprising forming an insulating etch stop layer over the metal lines before forming the second ILD layer.
9. A method for creating a fully-aligned via (FAV) by employing selective metal deposition, the method comprising:
forming metal lines within a first inter-layer dielectric (ILD) layer;
forming an insulating etch stop layer over the metal lines;
forming a second ILD layer over the insulating etch stop layer;
forming a lithographic stack over the second ILD layer to define areas where via growth is prevented;
recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack;
performing metal growth over the exposed top surface of the metal lines where via growth is permitted; and
depositing a conformal metal nitride cap over the metal growth such that airgaps are formed between the metal growth and the second ILD layer.
10. The method of claim 9 , further comprising removing the lithographic stack before depositing the metal growth.
11. The method of claim 10 , further comprising removing the exposed top surface of the conformal metal nitride cap over the metal growth to expose a top surface of the metal growth.
12. The method of claim 11 , further comprising performing single damascene metallization over the exposed top surface of the metal growth.
13. The method of claim 12 , wherein the metal growth is one or more self-aligned via interconnect structures.
14. The method of claim 9 , wherein the lithographic stack includes at least two sacrificial layer and an organic planarization layer.
15. The method of claim 14 , wherein the lithographic stack further includes an anti-reflective coating layer and a photoresist layer.
16. A semiconductor structure for creating a fully-aligned via (FAV) by employing selective metal deposition, the semiconductor structure comprising:
metal lines disposed within a first inter-layer dielectric (ILD) layer;
a second ILD layer disposed over the first ILD layer;
a metal growth disposed over exposed metal lines where via growth is permitted; and
a conformal metal nitride cap disposed over the metal growth such that airgaps are formed between the metal growth and the second ILD layer.
17. The semiconductor structure of claim 16 , wherein an insulating etch stop layer is disposed over the metal lines before depositing the second ILD layer.
18. The semiconductor structure of claim 17 , wherein a conductive material is disposed over the metal growth by employing single damascene metallization.
19. The semiconductor structure of claim 18 , wherein the conductive material, the metal growth, and the exposed metal lines are aligned.