Electronic device and method for data processing using virtual register mode

1. A method for operating a data processing device comprising:

supplying first input data to a first input of an execution unit of the data processing device, wherein the first input data is supplied by a first temporary register coupled to the first input of the execution unit;

applying, by the execution unit, a first processing operation on the first input data to generate, as an output of the execution unit, first output data;

determining an operation mode based on a control signal provided by switch control logic of the data processing device;

when the control signal indicates a first operation mode:

enabling a first feedback path and not a second feedback path; and

storing the first output data in a register of a register file of the data processing device;

wherein the first feedback path supplies the output of the execution unit to a data input of the register file and the second feedback path supplies the output of the execution unit to an input of the first temporary register;

when the control signal indicates a second operation mode:

enabling the first and second feedback paths;

storing the first output data in a register of the register file; and

storing the first output data in the first temporary register;

when the control signal indicates a third operation mode:

enabling the second feedback path but not the first feedback path; and

storing the first output data in the first temporary register; and

switching off a first clock signal supplied to the register file when the control signal indicates the third operation mode in which the first feedback path is not enabled.

2. The method of claim 1 , further comprising:

after storing the first output data in first temporary register in response to the control signal indicating either the second operation mode or the third operation mode:

supplying the first output data from the first temporary register as second input data to the first input of the execution unit; and

applying, by the execution unit, a second processing operation on the second input data to generate, as the output of the execution unit, second output data.

3. The method of claim 2 , further comprising:

determining an operation mode based on a subsequent control signal provided by the switch control logic;

when the subsequent control signal indicates the first operation mode:

enabling the first feedback path and not the second feedback path; and

storing the second output data in a register of the register file;

when the subsequent control signal indicates the second operation mode:

enabling the first and second feedback paths;

storing the second output data in a register of the register file; and

storing the second output data in the first temporary register;

when the control signal indicates the third operation mode:

enabling the second feedback path but not the first feedback path; and

storing the second output data in the first temporary register.

4. The method of claim 1 , further comprising:

controlling a switch in response to the control signal, wherein:

when the control signal indicates the first operation mode:

controlling the switch to couple the output of the execution unit to the data input of the register file;

when the control signal indicates the second operation mode:

controlling the switch to couple the output of the execution unit to the data input of the register file and to the input of the first temporary register file; and

when the control signal indicates the third operation mode:

controlling the switch to couple the output of the execution unit to the input of the first temporary register file.

5. The method of claim 1 , wherein the third operation mode is a virtual register mode in which the first output data bypasses the register file.

6. The method of claim 1 , wherein, when the control signal indicates the third operation mode, operation of the execution unit cannot be interrupted.

7. The method of claim 1 , further comprising supplying a second clock signal to the first temporary register.

8. The method of claim 7 , wherein the first and second clock signals have the same frequency but different phases.

9. The method of claim 7 , wherein the first and second clock signals have the same frequency and phase.

10. The method of claim 1 , further comprising:

concurrent with supplying the first input data to the first input of the execution unit, supplying second input data to a second input of the execution unit, the second input data supplied by a second temporary register, wherein the first processing operation to generate the first output data is applied on the first input data and the second input data, and wherein the second feedback path also supplies the output of the execution unit to an input of the second temporary register; and

storing the first output data in the second temporary register when the control signal indicates the second or third operation modes.

11. The method of claim 1 , further comprising:

in response to the control signal indicating either the second operation mode or the third operation mode in which the second feedback path is enabled:

supplying the first output data to a first input of a multiplexer having an output coupled to the input of the first temporary register; and

supplying a multiplexer control signal to cause the output of the multiplexer to supply the first output data to the input of the first temporary register.

12. The method of claim 1 , wherein the execution unit is an arithmetic logic unit (ALU).

13. The method of claim 1 , wherein the execution unit is a barrel shifter.

14. The method of claim 1 , wherein the execution unit is a multiplier unit.

15. The method of claim 1 , wherein the execution unit is an address calculation unit.

16. The method of claim 1 , wherein the data processing device is a digital signal processor.