Semiconductor device and system provided with a communication interface

1. A semiconductor device comprising:

an interface circuit operable to perform a sequential communication of transmit or receive according to a synchronous clock,

wherein the interface circuit comprises:

a first register operable to specify an operation enabled state which is enabling at least one of a transmit state and a receive state; and

a mode control circuit operable to change at least one mode of transmit or receive in the operation enabled state according to generated information to change the at least one mode of the interface circuit at a time of data transfer, based on data transfer information or contents of the data transfer, and

wherein the mode control circuit changes among modes of a transmit and receive mode, a transmit mode, and a receive mode while in the operation enabled state.

2. The semiconductor device according to claim 1 ,

wherein the interface circuit outputs a status, in response to a change of the mode.

3. The semiconductor device according to claim 1 further comprising:

a second register operable to hold information to specify a transmit determent or a receive determent, in a transmit and/or receive state.

4. The semiconductor device according to claim 3 ,

wherein the second register holds information capable of specifying one of command receive and data receive.

5. The semiconductor device according to claim 1 ,

wherein the interface circuit is capable of outputting one of a data transmit completion interruption request, a command receive completion interruption request, and a data receive completion interruption request.

6. The semiconductor device according to claim 1 further comprising:

a data transfer device,

wherein the mode control circuit is controlled corresponding to a prescribed operation of the data transfer device, and changed to the at least one mode after the completion of a transmit operation or a receive operation, and

wherein the mode of data transfer of at least transmit and receive is transitioned while in the transmit or receive state.

7. The semiconductor device according to claim 5 further comprising:

a data transfer device,

wherein the data transfer device is activated in response to one of the data transmit completion interruption request, the command receive completion interruption request, and the data receive completion interruption request.

8. The semiconductor device according to claim 7 ,

wherein the data transfer device comprises:

a register operable to store transfer mode information;

a register operable to store first source address information and second source address information;

a register operable to store destination address information; and

an arithmetic circuit, and

wherein the data transfer device performs a read, based on the result of arithmetic computations performed by the arithmetic circuit on data read based on the first source address information and the second source address information, and performs a write, based on the destination address information.

9. The semiconductor device according to claim 1 further comprising:

a central processing unit;

an interrupt control circuit; and

a data transfer device,

wherein the interface circuit makes an interruption request to the interrupt control circuit, and

wherein, in response to the interruption request, the interrupt control circuit outputs an interrupt signal to the central processing unit or outputs a start request to the data transfer device.

10. A system comprising:

a first semiconductor device including a first interface circuit operable to perform a sequential communication of transmit or receive according to a synchronous clock; and

a second semiconductor device including a second interface circuit operable to perform a sequential communication of transmit or receive according to the synchronous clock,

wherein the second interface circuit comprises:

a first register operable to specify a transmit and/or receive state; and

a mode control circuit operable to change at least one mode of transmit or receive in an operation enabled state enabling the specified transmit and/or receive state according to generated information to change the at least one mode of the second interface circuit at a time of data transfer, based on data transfer information or contents of the data transfer, and

wherein the mode control circuit changes among modes of a transmit and receive mode, a transmit mode, and a receive mode while in the operation enabled state.

11. The system according to claim 10 ,

wherein the second interface circuit outputs a status, in response to a change of the mode, and

wherein the first interface circuit inputs the status.

12. The system according to claim 10 ,

wherein the second interface circuit further comprises:

a second register operable to hold information to specify a transmit determent or a receive determent, in the transmit and/or receive state.

13. The system according to claim 12 ,

wherein the second register holds information capable of specifying one of command receive and data receive.

14. The system according to claim 10 ,

wherein the second interface circuit performs the sequential communication of transmit or receive in synchronization with one synchronous clock outputted from the first interface circuit.

15. The system according to claim 10 ,

wherein the second semiconductor device further comprises:

a data transfer device, and

wherein the mode control circuit is controlled corresponding to a prescribed operation of the data transfer device, and changes the mode after the completion of a transmit operation or a receive operation.

16. The system according to claim 10 ,

wherein the second semiconductor device further comprises:

a data transfer device, and

wherein the data transfer device is activated in response to one of a data transmit completion interruption request, a command receive completion interruption request, and a data receive completion interruption request, made by the second interface circuit.

17. The system according to claim 16 ,

wherein the data transfer device comprises:

a register operable to store transfer mode information;

a register operable to store first source address information and second source address information;

a register operable to store destination address information; and

an arithmetic circuit, and

wherein the data transfer device performs a read based on the result of arithmetic computations performed by the arithmetic circuit on data read based on the first source address information and the second source address information, and performs a write based on the destination address information.

18. The system according to claim 10 ,

wherein the second semiconductor device further comprises:

a central processing unit;

an interrupt control circuit; and

a data transfer device,

wherein the second interface circuit makes an interruption request to the interrupt control circuit, and

wherein, in response to the interruption request, the interrupt control circuit outputs an interrupt signal to the central processing unit or outputs a start request to the data transfer device.