Semiconductor structure and manufacturing method thereof
A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.
1. A semiconductor structure, comprising:
a substrate, having a first side and a second side opposite to each other;
a bipolar junction transistor (BJT), located at the first side of the substrate and comprising:
a collector, disposed in the substrate;
a base, disposed on the substrate; and
an emitter, disposed on the base;
a first interconnect structure, located at the first side of the substrate and electrically connected to the base; and
a second interconnect structure, located at the second side of the substrate and electrically connected to the collector, wherein
the first interconnect structure further extends to the second side of the substrate,
the first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side of the substrate,
the substrate comprises an insulating layer and a semiconductor layer located on the insulating layer, and the collector is disposed in the semiconductor layer.
2. The semiconductor structure according to claim 1 , further comprising:
a third interconnect structure, located at the first side of the substrate and electrically connected to the emitter, wherein the third interconnect structure further extends to the second side of the substrate, and the third interconnect structure is electrically connected to the external circuit at the second side of the substrate.
3. The semiconductor structure according to claim 1 , further comprising:
a complementary metal oxide semiconductor (CMOS) device, located at the first side of the substrate and comprising an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor, wherein
the NMOS transistor comprises:
a first conductive layer, disposed on the substrate;
a first dielectric layer, disposed between the first conductive layer and the substrate; and
a first N-type doped region and a second N-type doped region, disposed in the substrate at two sides of the first conductive layer, and
the PMOS transistor comprises:
a second conductive layer, disposed on the substrate;
a second dielectric layer, disposed between the second conductive layer and the substrate; and
a first P-type doped region and a second P-type doped region, disposed in the substrate at two sides of the second conductive layer.
4. The semiconductor structure according to claim 3 , further comprising:
a fourth interconnect structure, located at the first side of the substrate and electrically connected to the first conductive layer;
a fifth interconnect structure, located at the first side of the substrate and electrically connected to the first N-type doped region;
a sixth interconnect structure, located at the second side of the substrate and electrically connected to the second N-type doped region;
a seventh interconnect structure, located at the first side of the substrate and electrically connected to the second conductive layer;
an eighth interconnect structure, located at the first side of the substrate and electrically connected to the first P-type doped region; and
a ninth interconnect structure, located at the second side of the substrate and electrically connected to the second P-type doped region, wherein
the fourth interconnect structure, the fifth interconnect structure, seventh interconnect structure and eighth interconnect structure further extend to the second side of the substrate, and
the fourth interconnect structure to the ninth interconnect structure are respectively electrically connected to the external circuit at the second side of the substrate.
5. The semiconductor structure according to claim 3 , further comprising:
a high resistivity material layer, disposed over the CMOS device and the BJT.
6. The semiconductor structure according to claim 5 , wherein a resistivity of the high resistivity material layer is greater than 4000 Ω·cm.
7. The semiconductor structure according to claim 1 , wherein the BJT comprises a heterojunction bipolar transistor (HBT).
8. The semiconductor structure according to claim 1 , wherein the collector and the emitter have a first conductive type, and the base has a second conductive type.
9. The semiconductor structure according to claim 8 , wherein the collector comprises:
a heavily doped region, located in the substrate; and
a lightly doped region, located in the substrate between the heavily doped region and the base.
10. The semiconductor structure according to claim 8 , further comprising:
a first doped region and a second doped region, located in the base at two sides of the emitter and having the second conductive type, wherein
the first interconnect structure is electrically connected to the first doped region or the second doped region.
11. A method of manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate has a first side and a second side opposite to each other;
forming a BJT at the first side of the substrate, wherein the BJT comprises:
a collector, disposed in the substrate;
a base, disposed on the substrate; and
an emitter, disposed on the base;
forming a first interconnect structure electrically connected to the base at the first side of the substrate; and
forming a second interconnect structure electrically connected to the collector at the second side of the substrate, wherein
the first interconnect structure further extends to the second side of the substrate,
the first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side of the substrate,
the substrate comprises an insulating layer and a semiconductor layer located on the insulating layer, and the collector is disposed in the semiconductor layer.
12. The method of manufacturing the semiconductor structure according to claim 11 , further comprising:
forming a third interconnect structure electrically connected to the emitter at the first side of the substrate, wherein the third interconnect structure further extends to the second side of the substrate, and the third interconnect structure is electrically connected to the external circuit at the second side of the substrate.
13. The method of manufacturing the semiconductor structure according to claim 11 , further comprising:
forming a CMOS device at the first side of the substrate, wherein the CMOS device comprises an NMOS transistor and a PMOS transistor,
the NMOS transistor comprises:
a first conductive layer, disposed on the substrate;
a first dielectric layer, disposed between the first conductive layer and the substrate; and
a first N-type doped region and a second N-type doped region, disposed in the substrate at two sides of the first conductive layer, and
the PMOS transistor comprises:
a second conductive layer, disposed on the substrate;
a second dielectric layer, disposed between the second conductive layer and the substrate; and
a first P-type doped region and a second P-type doped region, disposed in the substrate at two sides of the second conductive layer.
14. The method of manufacturing the semiconductor structure according to claim 13 , further comprising:
forming a fourth interconnect structure electrically connected to the first conductive layer at the first side of the substrate;
forming a fifth interconnect structure electrically connected to the first N-type doped region at the first side of the substrate;
forming a sixth interconnect structure electrically connected to the second N-type doped region at the second side of the substrate;
forming a seventh interconnect structure electrically connected to the second conductive layer at the first side of the substrate;
forming an eighth interconnect structure electrically connected to the first P-type doped region at the first side of the substrate; and
forming a ninth interconnect structure electrically connected to the second P-type doped region at the second side of the substrate, wherein
the fourth interconnect structure, the fifth interconnect structure, seventh interconnect structure and eighth interconnect structure further extend to the second side of the substrate, and
the fourth interconnect structure to the ninth interconnect structure are respectively electrically connected to the external circuit at the second side of the substrate.
15. The method of manufacturing the semiconductor structure according to claim 13 , further comprising:
forming a high resistivity material layer above the CMOS device and the BJT.
16. The method of manufacturing the semiconductor structure according to claim 15 , wherein the substrate comprises a semiconductor on insulator (SOI) substrate, and the SOI substrate comprises:
a substrate layer;
the insulating layer, disposed on the substrate layer; and
the semiconductor layer, located on the insulating layer, wherein
the substrate layer is removed after the high resistivity material layer is formed.
17. The method of manufacturing the semiconductor structure according to claim 11 , wherein the collector and the emitter have a first conductive type, and the base has a second conductive type.
18. The method of manufacturing the semiconductor structure according to claim 17 , wherein a method of forming the collector comprises:
forming a heavily doped region in the substrate; and
forming a lightly doped region in the substrate between the heavily doped region and the base.
19. The method of manufacturing the semiconductor structure according to claim 17 , further comprising:
forming a first doped region and a second doped region in the base at two sides of the emitter, wherein the first doped region and the second doped region have the second conductive type, and
the first interconnect structure is electrically connected to the first doped region or the second doped region.