Delay cell and circuit including the same

1. A delay cell comprising:

a first inverter coupled to an input terminal;

a second inverter coupled between the first inverter and an output terminal;

a plurality of additional inverters coupled in parallel to the first inverter; and

a delay element suitable for selectively coupling the additional inverters to the input terminal under control of a control signal.

2. The delay cell of claim 1 , wherein the delay element comprises a switching element, which is switched on under control of the control signal, and couples the additional inverter to the input terminal.

3. The delay cell of claim 2 , wherein the switching element comprises a transfer gate, which is turned on under control of the control signal, and couples the additional inverter to the input terminal.

4. The delay cell of claim 1 , wherein the plurality of additional inverters operate based on a plurality of enable signals, respectively.

5. A delay circuit comprising:

at least one delay cell suitable for delaying an input signal applied to an input terminal, and outputting the delayed input signal as an output signal through an output terminal; and

a signal generation circuit suitable for generating a control signal for controlling the delay of the input signal,

wherein the delay cell comprises:

a first inverter coupled to the input terminal;

a second inverter coupled between the first inverter and the output terminal;

a plurality of additional inverters coupled in parallel to the first inverter; and

a delay element suitable for selectively coupling one or more of the additional inverters to the input terminal under control of the control signal.

6. The delay circuit of claim 5 , wherein the delay element comprises a plurality of switching elements, which couple the corresponding inverters of the additional inverters to the input terminal, based on a plurality of enable signals included in the control signal, respectively.

7. The delay circuit of claim 6 , wherein each of the switching elements comprises a transfer gate, which is turned on based on the corresponding enable signal among the plurality of enable signals, and couples the corresponding inverter of the additional inverters to the input terminal.

8. The delay circuit of claim 6 , wherein the signal generation circuit generates the plurality of enable signals to operate only a near inverter close to the first inverter, among the plurality of additional inverters, when a required delay value is small.

9. The delay circuit of claim 8 , wherein the signal generation circuit generates the plurality of enable signals to sequentially operate the remaining inverters after the near inverter, among the plurality of additional inverters, as the required delay value is increased.