Real-time resource handling in resource retry queue

1. An apparatus, comprising:

a plurality of transaction buffers, each configured to store a plurality of memory transactions;

a retry queue circuit configured to store one or more entries corresponding to one or more memory transactions, wherein a position in the retry queue circuit of a particular entry of the one or more entries corresponds to a priority for processing a memory transaction corresponding to the particular entry;

a transaction arbiter circuit configured to:

receive a real-time memory transaction from a particular transaction buffer of the plurality of transaction buffers;

in response to a determination that the real-time memory transaction is unable to be processed, create an entry for the real-time memory transaction in the retry queue circuit; and

in response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, upgrade the bulk memory transaction to use real-time memory resources, wherein the real-time memory transaction has a higher priority than the bulk memory transaction.

2. The apparatus of claim 1 , wherein an entry for the bulk memory transaction is in an initial position, and wherein the transaction arbiter circuit is further configured to create the entry for the real-time memory transaction in a position next to the initial position in the retry queue circuit, in response to a determination that one or more resources to be used by the real-time memory transaction are currently unavailable, wherein the initial position of the retry queue circuit corresponds to a highest priority position.

3. The apparatus of claim 1 , wherein the transaction arbiter circuit is further configured to release one or more resources allocated to the bulk memory transaction prior to the upgrade of the bulk memory transaction.

4. The apparatus of claim 1 , wherein the transaction arbiter circuit is further configured to reset an age of the upgraded bulk memory transaction.

5. The apparatus of claim 1 , wherein the transaction arbiter circuit is further configured to upgrade the bulk memory transaction to use real-time memory resources, in response to a determination that the bulk memory transaction and the real-time memory transaction both target a same address.

6. The apparatus of claim 5 , wherein the transaction arbiter circuit is further configured to:

determine that a second bulk memory transaction is scheduled to be processed prior to the upgraded bulk memory transaction; and

in response to a determination that the upgraded bulk memory transaction has been processed and the second bulk memory transaction has not been processed, upgrade the second bulk memory transaction to use real-time memory resources.

7. The apparatus of claim 1 , further comprising a transaction pipeline configured to process memory transactions, wherein the transaction arbiter circuit is further configured to create the entry for the real-time memory transaction in response to a determination that a blocking memory transaction is in the transaction pipeline, wherein the transaction pipeline is further configured to upgrade the blocking memory transaction to use real-time memory resources in response to the creation of the entry for the real-time memory transaction, and wherein the blocking memory transaction and the real-time memory transaction both target a same address.

8. A method, comprising:

receiving a real-time memory transaction from a particular transaction buffer of a plurality of transaction buffers, wherein the real-time memory transaction has a higher priority than a bulk memory transaction;

in response to determining that the real-time memory transaction is unable to be processed, creating an entry for the real-time memory transaction in a retry queue circuit; and

in response to determining that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, upgrading the bulk memory transaction to use real-time memory resources.

9. The method of claim 8 , further comprising releasing one or more resources allocated to the bulk memory transaction prior to the upgrade of the bulk memory transaction.

10. The method of claim 8 , further comprising resetting an age of the upgraded bulk memory transaction.

11. The method of claim 8 , wherein determining that the real-time memory transaction is unable to be processed comprises determining that one or more resources to be used by the real-time memory transaction are currently unavailable.

12. The method of claim 11 , further comprising creating the entry for the real-time memory transaction in a position next to an initial position in the retry queue circuit that is occupied by the bulk memory transaction, wherein the initial position of the retry queue circuit corresponds to a highest priority position.

13. The method of claim 8 , wherein determining that the real-time memory transaction is unable to be processed comprises determining that the bulk memory transaction and the real-time memory transaction both target a same address, wherein the bulk memory transaction comes before the real-time memory transaction in program order.

14. The method of claim 13 , further comprising upgrading the bulk memory transaction to use real-time memory resources, in response to a determination that the bulk memory transaction and the real-time memory transaction both target a same address.

15. The method of claim 14 , further comprising:

determining that a second bulk memory transaction that is scheduled to be processed prior to the upgraded bulk memory transaction also targets the same address; and

in response to determining that the upgraded bulk memory transaction has been processed and the second bulk memory transaction has not been processed, upgrading the second bulk memory transaction to use real-time memory resources.

16. A system, comprising:

one or more processing cores configured to issue a plurality of memory transactions with one of at least a bulk priority level or a real-time priority level, wherein the real-time priority level has a higher priority than the bulk priority level; and

a memory cache controller configured to:

receive a real-time memory transaction from a particular processing core of the one or more processing cores;

in response to a determination that the real-time memory transaction is unable to be processed, create an entry for the real-time memory transaction in a retry queue circuit included in the memory cache controller; and

in response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, upgrade the bulk memory transaction to use real-time memory resources.

17. The system of claim 16 , wherein the memory cache controller is further configured to release one or more resources allocated to the bulk memory transaction prior to the upgrade of the bulk memory transaction.

18. The system of claim 16 , wherein the memory cache controller is further configured to reset an age of the upgraded bulk memory transaction.

19. The system of claim 16 , wherein to determine that the real-time memory transaction is unable to be processed, the memory cache controller is further configured to determine that one or more resources to be used by the real-time memory transaction are currently unavailable.

20. The system of claim 16 , wherein to determine that the real-time memory transaction is unable to be processed, the memory cache controller is further configured to determine that the bulk memory transaction and the real-time memory transaction both target a same address, wherein the bulk memory transaction comes before the real-time memory transaction in program order.