Circuit for fingerprint sensing and electronic device comprising the circuit
A circuit for fingerprint detection is disclosed. The circuit includes a transistor and a capacitor. The transistor includes a gate configured to, in response to a touch event of an object, sense a capacitance associated with the object. The capacitor, coupled between a first node and a second node, is configured to establish a voltage across the first node and the second node in response to a first control signal, and establish a compensation voltage at the first node in response to a second control signal. The transistor is configured to flow a current therethrough in response to a third control signal. The current has a magnitude independent of the threshold voltage of the transistor due to the compensation voltage.
1. A circuit, comprising:
a transistor including a gate configured to, in response to a touch event of an object, sense a capacitance associated with the object; and
a capacitor, coupled between a first node and a second node, the first node coupled to the gate of the transistor, the capacitor configured to establish a voltage across the first node and the second node in response to a first control signal, the voltage equal to a threshold voltage of the transistor, and establish a compensation voltage at the first node in response to a second control signal,
wherein the transistor is configured to flow a current therethrough in response to a third control signal, the current having a magnitude independent of the threshold voltage of the transistor due to the compensation voltage.
2. The circuit according to claim 1 , wherein the transistor includes a first terminal configured to receive a supply voltage, and the compensation voltage equals to the supply voltage minus the threshold voltage of the transistor.
3. The circuit according to claim 2 , wherein the magnitude of the current is zero.
4. The circuit according to claim 1 further comprising a first transistor including a gate to receive the third control signal, a first terminal to receive a reference voltage, and a second terminal coupled to the second node of the capacitor.
5. The circuit according to claim 4 , wherein the transistor includes a first terminal configured to receive a supply voltage, and a difference made in a voltage at the first node in response to the third control signal is expressed as:
Δ
V
A
=
(
VDD
-
Vref
)
×
[
Cfinger
C
1
+
C
finger
]
where ΔVA represents the difference made in the voltage at the first node, VDD represents the supply voltage, Vref represents the reference voltage, C 1 represents a capacitance of the capacitor, and Cfinger represents the capacitance associated with the object.
6. The circuit according to claim 5 , wherein a difference made in the current in response to the third control signal is positively proportional to the ΔVA squared and is expressed as:
Δ
Ids
3
∝
[
(
VDD
-
Vref
)
×
(
Cfinger
C
1
+
C
finger
)
]
2
where Δ|Ids 3 | represents the difference made in the current.
7. The circuit according to claim 1 , wherein the transistor includes a first terminal configured to receive a supply voltage, further comprising a second transistor including a gate to receive the third control signal, a first terminal coupled to a second terminal of the transistor, and a second terminal to output the current flowing through the transistor.
8. The circuit according to claim 1 further comprising a fourth transistor including a gate to receive the first control signal, a first terminal to receive a supply voltage, and a second terminal coupled to the first node.
9. The circuit according to claim 1 further comprising a fifth transistor including a gate to receive the first control signal, a first terminal to receive the second control signal, and a second terminal coupled to the second node.
10. The circuit according to claim 1 further comprising a sixth transistor including a gate to receive the second control signal, a first terminal to receive a supply voltage, and a second terminal coupled to the second node.
11. The circuit according to claim 1 further comprising a sixth transistor including a gate to receive the second control signal, a first terminal to receive the first control signal, and a second terminal coupled to the second node.
12. The circuit according to claim 1 further comprising a sixth transistor including a gate to receive the second control signal, a first terminal to receive the third control signal, and a second terminal coupled to the second node.
13. The circuit according to claim 1 , wherein the transistor includes a first terminal configured to receive a supply voltage, further comprising a seventh transistor including a gate to receive the second control signal, a first terminal coupled to the first node, and a second terminal coupled to a second terminal of the transistor.
14. An electronic device, comprising:
an array of sensor units, each of the sensor units comprising:
a transistor including a gate configured to, in response to a touch event of an object, sense a capacitance associated with the object, and
a capacitor, coupled between a first node and a second node, the first node coupled to the gate of the transistor, the capacitor configured to establish a voltage across the first node and the second node in response to a first control signal, the voltage equal to a threshold voltage of the transistor, and establish a compensation voltage at the first node in response to a second control signal,
wherein the transistor is configured to flow a current therethrough in response to a third control signal, the current having a magnitude independent of the threshold voltage of the transistor due to the compensation voltage.
15. The electronic device according to claim 14 , wherein the transistor includes a first terminal configured to receive a supply voltage, and the compensation voltage equals to the supply voltage minus the threshold voltage of the transistor.
16. The electronic device according to claim 15 , wherein the magnitude of the current is zero.
17. The electronic device according to claim 14 further comprising a first transistor including a gate to receive the third control signal, a first terminal to receive a reference voltage, and a second terminal coupled to the second node of the capacitor.
18. The electronic device according to claim 17 , wherein the transistor includes a first terminal configured to receive a supply voltage, and a difference made in a voltage at the first node in response to the third control signal is expressed as:
Δ
V
A
=
(
VDD
-
Vref
)
×
[
Cfinger
C
1
+
C
finger
]
where ΔVA represents the difference made in the voltage at the first node, VDD represents the supply voltage, Vref represents the reference voltage, C 1 represents a capacitance of the capacitor, and Cfinger represents the capacitance associated with the object.
19. The electronic device according to claim 18 , wherein a difference made in the current in response to the third control signal is positively proportional to the ΔVA squared and is expressed as:
Δ
Ids
3
∝
[
(
VDD
-
Vref
)
×
(
Cfinger
C
1
+
C
finger
)
]
2
where Δ|Ids 3 | represents the difference made in the current.