Low-voltage reference current circuit

1. A current reference circuit comprising:

a current source;

a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source;

an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the drain of the first PMOS transistor; and

a first resistive element having a first terminal coupled to a source of the NMOS transistor and a gate of the first PMOS transistor and a second terminal coupled to a ground potential.

2. The current reference circuit of claim 1 , wherein the first supply voltage is an input/output (TO) supply voltage, and the second supply voltage is a core voltage, the second supply voltage being lower than the first supply voltage.

3. The current reference circuit of claim 1 , further comprising:

a second PMOS transistor having a drain coupled to the first supply voltage;

a second resistive element having a first terminal coupled to the first terminal of the first resistive element and a second terminal coupled to the gate of the second PMOS transistor.

4. The current reference circuit of claim 3 , further comprising:

a capacitive element having a first terminal coupled to the first supply voltage and a second terminal coupled to the second terminal of the second resistive element.

5. The current reference circuit of claim 1 , wherein the first supply voltage is about 0.9V to 1.0V, and the second supply voltage is about 0.6V.

6. The current reference circuit of claim 5 , wherein the gate of the NMOS transistor has a voltage about 0.4V, and the gate of the first PMOS transistor has a voltage about 0.1V.

7. The current reference circuit of claim 6 , wherein the current source has a current about 10 μA, and a current flowing through the first resistive element is about 10 nA.

8. The current reference circuit of claim 1 , wherein the NMOS transistor is a native transistor having a threshold voltage equal to or less than 0.1 V.

9. A current mirror comprising:

a current source;

a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source;

a second PMOS transistor having a source coupled to the first supply voltage, a gate coupled to the gate of the first PMOS transistor, and a drain configured to provide a second current source; and

an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the current source, and a source coupled to the gate of the first PMOS transistor.

10. The current mirror of claim 9 , further comprising:

a first resistive element coupled between the source of the NMOS transistor and a ground potential;

a second resistive element coupled between the gate of the first PMOS transistor and the gate of the second PMOS transistor; and

a capacitive element coupled between the first supply voltage and the gate of the second PMOS transistor.

11. The current mirror of claim 10 , wherein the first supply voltage is about 0.9V to 1.0V, and the second supply voltage is about 0.6V.

12. The current mirror of claim 11 , wherein the gate of the NMOS transistor has a voltage about 0.4V, and the gate of the first PMOS transistor has a voltage about 0.1V.

13. The current mirror of claim 12 , wherein the current source has a current about 10 μA, and a current flowing through the first resistive element is about 10 nA.

14. The current mirror of claim 10 , wherein the second resistive element has a resistance value of about 10 MΩ.

15. The current mirror of claim 9 , wherein the NMOS transistor is a low threshold voltage transistor having a threshold voltage of about 0.3V.

16. The current mirror of claim 9 , wherein the NMOS transistor is a native NMOS transistor.

17. An integrated current reference circuit comprising:

a first voltage source;

a voltage offset circuit having a first end and a second end;

a reference current having one end coupled to the second end of the voltage offset circuit and another end coupled to a ground potential;

a first p-channel transistor having a source coupled to the first voltage source, a gate coupled to the first end of the voltage offset circuit, and a drain coupled to the reference current;

a second p-channel transistor having a source coupled to the first voltage source, a gate coupled to the first end of the voltage offset circuit, and a drain configured to provide an output current,

wherein the voltage offset circuit comprises:

a second voltage source;

an n-channel transistor having a drain coupled to the second voltage source, a gate coupled to the drain of the first p-channel transistor, and a source coupled to the gate of the first p-channel transistor; and

a first resistor coupled between the source of the n-channel transistor and a ground potential.

18. The integrated current reference circuit of claim 17 , further comprising:

a second resistor coupled between the gate of the first p-channel transistor and the gate of the second p-channel transistor; and

a capacitor coupled between the first voltage source and the gate of the second p-channel transistor.

19. The integrated current reference circuit of claim 17 , wherein the first p-channel transistor and the second p-channel transistor each have a first threshold voltage, and the n-channel transistor has a second threshold voltage that is lower than the first threshold voltage.

20. The integrated current reference circuit of claim 17 , wherein the n-channel transistor is a native transistor having a threshold voltage equal to or less than 0.1 V.