IP Library Granted Patent US 10,433,320
Granted Patent B2
US 10,433,320 · App. 15/531,222 · Granted Oct 1, 2019

Switching and synchronization device

Inventor: Nishiki Mizusawa (Kanagawa, JP)
Assignee: SONY CORPORATION
H04W72/12H04L5/14H04W28/06H04W56/00H04W72/04
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Quick Facts
Patent No.
US 10,433,320
App. No.
15/531,222
Granted
Oct 1, 2019
Kind
B2
Abstract

To enable radio communication to be performed more favorably in a UL band of FDD when the UL band is used for both DL and UL in a time division manner. There is provided a device that includes a switching unit that switches an operation mode of an uplink band of FDD between a first mode in which the uplink band is used for uplink and a second mode in which the uplink band is used for both downlink and uplink in a time division manner and a control unit that gives an instruction on a first timing advance on the basis of a downlink reception timing in a downlink band of FDD corresponding to the uplink band and an instruction on a second timing advance on the basis of a downlink reception timing in the uplink band.

Claims (24)

1. A device, comprising:

a processor configured to:

switch an operation mode of an uplink band of frequency division duplex (FDD) between a first mode in which the uplink band is used for uplink and a second mode in which the uplink band is used for both downlink and the uplink in a time division manner; and

give a first instruction on a first timing advance based on a downlink reception timing in a downlink band of the FDD corresponding to the uplink band and a second instruction on a second timing advance based on a downlink reception timing in the uplink band.

2. The device according to claim 1 , wherein the processor is further configured to give the first instruction on the first timing advance and the second instruction on the second timing advance when the operation mode is the second mode.

3. The device according to claim 1 , wherein the first instruction on the first timing advance and the second instruction on the second timing advance are instructions to a same terminal device that supports the second mode.

4. The device according to claim 3 , wherein the processor is further configured to give the first instruction on the first timing advance and the second instruction on the second timing advance based on reporting of a timing advance command.

5. The device according to claim 4 , wherein the timing advance command includes a first timing advance command for the first timing advance and a second timing advance command for the second timing advance.

6. The device according to claim 5 , wherein

the first timing advance command for the first timing advance is a command for a first timing advance group, and the second timing advance command for the second timing advance is a command for a second timing advance group that is different from the first timing advance group.

7. The device according to claim 3 , wherein the processor is further configured to:

give an instruction on one of the first timing advance or the second timing advance based on reporting of a timing advance command; and

give an instruction on the other of the first timing advance and the second timing advance based on reporting of information indicating an offset between the first timing advance and the second timing advance.

8. The device according to claim 1 , wherein

the first instruction on the first timing advance is an instruction to a first terminal device that does not support the second mode, and

the second instruction on the second timing advance is an instruction to a second terminal device that supports the second mode.

9. The device according to claim 8 , wherein

the first terminal device is configured to adjust an uplink transmission timing in the uplink band based on the downlink reception timing in the downlink band, and

the second terminal device is configured to adjust the uplink transmission timing in the uplink band based on the downlink reception timing in the uplink band when the operation mode is the second mode.

10. The device according to claim 1 , wherein the processor is further configured to transmit a synchronization signal in the uplink band when the operation mode is the second mode.

11. The device according to claim 10 , wherein

in the second mode the uplink band is used for both the downlink and the uplink in the time division manner and the uplink band is used for the downlink with at least a determined subframe of a radio frame, and

the processor is further configured to transmit the synchronization signal in the uplink band when the operation mode is the second mode such that the synchronization signal is transmitted in the determined subframe of the radio frame.

12. The device according to claim 1 , wherein the processor is further configured to report information indicating an uplink/downlink configuration for the uplink band to a terminal device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2017
From: MIZUSAWA, NISHIKI
To: SONY CORPORATION
Reel/Frame 042606/0821 →
Priority Claims (1)
JP 2014-251662 · Dec 12, 2014 · national
Continuity (1)
Related Publication 20170325248A1 · Nov 9, 2017