Integrated circuit for multiple patterning lithography, a computing system and a computer-implemented method for designing an integrated circuit

1. An integrated circuit, comprising:

a lower layer including first and second lower patterns extending in a first direction;

a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; and

an upper layer including first and second upper patterns, wherein the first upper pattern is arranged on the first via, the second upper pattern is arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, and the first and second upper patterns are adjacent to each other in a second direction perpendicular to the first direction,

wherein a width of the first lower pattern in the second direction is greater than a width of the first via in the second direction, and

the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region,

wherein a space between the first and second upper patterns is equal to or greater than a minimum space between patterns to which different colors are assigned.

2. The integrated circuit of claim 1 , wherein a width of the second lower pattern in the second direction is greater than a width of the second via in the second direction, and

the second via is arranged in a third edge region of the second lower pattern, the third edge region being farther away from the first lower pattern than a fourth edge region of the second lower pattern, the fourth edge region being opposite to the third edge region.

3. The integrated circuit of claim 2 , wherein the first edge region of the first lower pattern is adjacent to a first edge of the first lower pattern, wherein the first edge extends in the first direction, and the first edge is farther away from the second lower pattern than a second edge of the first lower pattern, the second edge being opposite to the first edge, and

the third edge region of the second lower pattern is adjacent to a third edge of the second lower pattern, wherein the third edge extends in the first direction, and the third edge is farther away from the first lower pattern than a fourth edge of the second lower pattern, the fourth edge being opposite to the third edge.

4. The integrated circuit of claim 2 , further comprising:

a first marking layer that marks a region of the first lower pattern, on which the first via is arranged, and is located on first the edge region of the first lower pattern; and

a second marking layer that marks a region of the second lower pattern, on which the second via is arranged, and is located on the third edge region of the second lower pattern.

5. The integrated circuit of claim 2 , further comprising:

a first obstacle marking layer that marks a prohibition region of the first via, on the first lower pattern, and is located on the second edge region of the first lower pattern; and

a second obstacle marking layer that marks a prohibition region of the second via, on the second lower pattern, and is located on the fourth edge region of the second lower pattern.

6. The integrated circuit of claim 1 , wherein the first and second upper patterns are located on a first track, and

the upper layer further includes third and fourth upper patterns which are located on a second track that is adjacent to the first track and extend in the second direction, and wherein a third color is assigned to the third upper pattern and a fourth color is assigned to the fourth upper pattern.

7. The integrated circuit of claim 1 , wherein the first and second upper patterns are located on a first track, and

the upper layer further includes a third upper pattern which is located on a second track that is adjacent to the first track and extends in the second direction, and wherein a third color is assigned to the third upper pattern.

8. The integrated circuit of claim 1 , wherein the lower layer further includes a third lower pattern extending in the first direction between the first and second lower patterns.

9. The integrated circuit of claim 8 , wherein a width of the first lower pattern in the second direction is greater than a width of the third lower pattern in the second direction.

10. The integrated circuit of claim 9 , wherein the width of the first lower pattern in the second direction and a width of the second lower pattern in the second direction are the same.

11. The integrated circuit of claim 9 , wherein the width of the first lower pattern in the second direction and a width of the second lower pattern in the second direction are different from each other.

12. The integrated circuit of claim 1 , further comprising:

first and second active regions having different conductive types and extending in the second direction; and

a plurality of gate lines extending in the first direction across the first and second active regions and arranged in parallel to one another,

wherein the lower layer and the upper layer are wiring layers arranged above the plurality of gate lines.

13. The integrated circuit of claim 12 , wherein the lower layer is a first metal layer arranged above the plurality of gate lines and electrically connected to the plurality of gate lines, and

the upper layer is a second metal layer arranged above the first metal layer and electrically connected to the first metal layer.

14. A semiconductor device, comprising:

a substrate;

a lower wiring layer including a left pattern and a right pattern arranged on the substrate to extend in a first direction;

a first via arranged on a left edge region of the left pattern, and a second via arranged on a right edge region of the right pattern; and

an upper wiring layer including first and second upper patterns extending in a second direction perpendicular to the first direction and adjacent to each other in the second direction, wherein the first upper pattern is formed on the first via and the second upper pattern is formed on the second via,

wherein a space between the first and second upper patterns is equal to or greater than a minimum space between patterns to which different colors are assigned.

15. The semiconductor device of claim 14 , wherein a width of the left pattern in the second direction is greater than a width of the first via in the second direction, and a width of the right pattern in the second direction is greater than a width of the second via in the second direction.

16. The semiconductor device of claim 14 , wherein the lower wiring layer further includes a central pattern extending in the first direction between the left pattern and the right pattern.

17. The semiconductor device of claim 16 , wherein a width of the left pattern or the right pattern in the second direction is greater than a width of the central pattern in the second direction.

18. The semiconductor device of claim 14 , wherein the substrate has first and second active regions having different conductive types and extending in the second direction,

the semiconductor device further comprising:

a plurality of gate lines extending in the first direction across the first and second active regions and arranged in parallel to one another,

wherein the lower wiring layer is a first metal layer arranged above the plurality of gate lines and electrically connected to the plurality of gate lines, and

the upper wiring layer is a second metal layer arranged above the first metal layer and electrically connected to the first metal layer.

19. An integrated circuit, comprising:

first and second patterns extending lengthwise in a first direction;

a first via disposed on the first pattern;

a second via disposed on the second pattern, wherein a distance separating the first and second vias in a second direction crossing the first direction is greater than a distance separating the first and second patterns from each other in the second direction;

a third pattern disposed on the first via, wherein the third pattern has a first color; and

a fourth pattern disposed on the second via, wherein the fourth pattern has a second color,

wherein a space between the third and fourth patterns is equal to or greater than a minimum space between patterns to which different colors are assigned.

20. The integrated circuit of claim 19 , wherein the first and second patterns are disposed in the same layer as each other, and the third and fourth patterns are disposed in the same layer as each other.