Optimal LDPC bit flip decision
A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.
1. A solid state storage device, comprising:
a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code (ECC) and a second Low Density Parity Check (LDPC) error-correcting code,
the non-volatile memory controller including a hard-decision LDPC decoder to decode encoded data received with errors from the non-volatile memory and provide a decoded data output, and
the hard-decision LDPC decoder selecting a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes,
wherein the voting scheme is configured to count a number of votes from each of the check nodes and the variable node to determine when to implement the bit flipping at the variable node, the determination based on an evaluation of a static relationship between the number of votes and a number of the plurality of check nodes connected to a variable node of the plurality of variable nodes.
2. The solid state storage device of claim 1 , wherein the hard-decision LDPC decoder reduces the number of errors in the decoded data to give partially decoded data containing errors where the first error-correcting code is capable of fully correcting the errors contained in the partially decoded data.
3. The solid state storage device of claim 2 , further comprising an ECC decoder which completely decodes the partially decoded data containing errors to give fully decoded data containing no errors.
4. The solid state storage device of claim 3 , wherein the ECC decoder is a Bose-Chaudhuri-Hocquenghem (BCH) decoder.
5. The solid state storage device of claim 1 , wherein the LDPC decoder selects the voting scheme based on majority voting with a vote count offset with an adjustment value.
6. The solid state storage device of claim 5 , wherein the adjustment value is dependent on an iteration sequence number of the iteration in the sequence of iterations used by the hard-decision LDPC decoder.
7. The solid state storage device of claim 5 , wherein the adjustment value is predetermined.
8. The solid state storage device of claim 5 , wherein the adjustment value for the first iteration is 1, the adjustment value for the last iteration is 0, and the adjustment value for each of the iterations between the first and last iterations is 1.
9. The solid state storage device of claim 1 , wherein the hard-decision LDPC decoder flips the vote on a variable node from a previous iteration when:
2 F>N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
10. The solid state storage device of claim 1 , wherein the hard-decision LDPC decoder retains the vote on a variable node from a previous iteration when:
2 F=N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
11. The solid state storage device of claim 1 , wherein the hard-decision LDPC decoder does not flip the vote on a variable node from a previous iteration when:
2 F<N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
12. A method of improving the decoding of data encoded with a first error-correcting code (ECC) and a second Low Density Parity Check (LDPC) error-correcting code, implemented in a non-volatile memory having a non-volatile memory controller configured to store data in the non-volatile memory, the method comprising:
selecting a voting scheme at each iteration in a sequence of iterations of a hard-decision LDPC decoder of the second LDPC error-correcting code to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes,
wherein the voting scheme is configured to count a number of votes from each of the check nodes and the variable node to determine when to implement the bit flipping at the variable node, the determination based on an evaluation of a static relationship between the number of votes and a number of the plurality of check nodes connected to a variable node of the plurality of variable nodes.
13. The method of claim 12 , wherein the hard-decision LDPC decoder reduces the number of errors in the decoded data to give partially decoded data containing errors which the first error-correcting code can correct.
14. The method of claim 13 , further comprising an ECC decoder which completely decodes the partially decoded data containing errors to give fully decoded data containing no errors.
15. The method of claim 14 , wherein the ECC decoder is a Bose-Chaudhuri-Hocquenghem (BCH) decoder.
16. The method of claim 12 , wherein the LDPC decoder selects the voting scheme based on majority voting with a vote count offset with an adjustment value.
17. The method of claim 16 , wherein the adjustment value is dependent on an iteration sequence number of each iteration in the sequence of iterations used by the hard-decision LDPC decoder.
18. The method of claim 16 , wherein the adjustment value is predetermined.
19. The method of claim 16 , wherein the adjustment value for the first iteration is 1, the adjustment value for the last iteration is 0, and the adjustment value for each of the iterations between the first and last iterations is 1.
20. The method of claim 12 , wherein the hard-decision LDPC decoder flips the vote on a variable node from a previous iteration when:
2 F>N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
21. The method of claim 12 , wherein the hard-decision LDPC decoder retains the vote on a variable node from a previous iteration when:
2 F=N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
22. The method of claim 12 , wherein the hard-decision LDPC decoder does not flip the vote on a variable node from a previous iteration when:
2 F<N+ 1+ V it
wherein
F is the number of votes to flip on the check nodes and the variable node connected to the check nodes,
N is the number of connected check nodes connected to a variable node, and
V it is an adjustment value at iteration it.
23. A solid state storage device, comprising:
a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) error-correcting code,
the non-volatile memory controller including:
a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory to generate partially decoded data containing errors which the first error-correcting code can correct, and
a decoder of the first error-correcting code that receives the partially decoded data containing errors and generates fully decoded data containing no errors, and
the hard-decision LDPC decoder selecting a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes,
wherein the decoder is configured to count a number of votes from each of the check nodes and the variable node to determine when to implement the bit flipping at the variable node, the determination based on an evaluation of a static relationship between the number of votes and a number of the plurality of check nodes connected to a variable node of the plurality of variable nodes.