4F2 resistive non-volatile memory formed in a NAND architecture
A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4F 2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.
1. A method for fabricating a memory device, comprising:
providing a substrate having a set of transistors formed in the substrate;
forming a set of metal lines over the substrate respectively connected to source or drain contacts of the transistors; and
forming a two-terminal switching device over the metal lines and connected at a first terminal to one of the metal lines and electrically connected at a second terminal to a second of the metal lines, thereby connecting the two-terminal switching device electrically in parallel with a transistor of the set of transistors; wherein the two-terminal switching device and the transistor form a 1T-1R memory cell that has a projected area on the substrate approximately equal to 4F 2 .
2. The method of claim 1 , further comprising forming a second set of metal lines over the two-terminal switching device, wherein one of the second set of metal lines is connected to and provides electrical protection between the second terminal of the two-terminal switching device and the second of the metal lines.
3. The method of claim 2 , further comprising forming a second two-terminal switching device over the second set of metal lines and offset about 1F distance from the two-terminal switching device.
4. The method of claim 3 , further comprising electrically connecting the second two-terminal switching device at a first end thereof to the second terminal of the two-terminal switching device and the one of the second set of metal lines.
5. The method of claim 4 , further comprising forming a set of third metal lines over the second switching device, connecting one of the third metal lines at a second end of the second two-terminal switching device, and electrically connecting the one of the third metal lines to a second of the second set of metal lines and to a third of the set of metal lines.
6. The method of claim 1 , further comprising electrically connecting a second two-terminal switching device in parallel to a second transistor of the set of transistors formed in the substrate thereby forming a second 1T-1R memory cell that has a second projected area approximately equal to 4F 2 and that is adjacent to the projected area.
7. The method of claim 1 , further comprising:
forming the two-terminal switching device as one of an array of two-terminal switching devices; and
forming a select transistor at a first end of the array of two-terminal switching devices, the select transistor configured to electrically connect or electrically isolate the array of two-terminal switching devices to or from a sourceline of the memory device.
8. The method of claim 7 , further comprising forming a second select transistor at a second end of the array of two-terminal switching devices, the second select transistor configured to electrically connect or electrically isolate the array of two-terminal switching devices to or from a bitline of the memory device.
9. The method of claim 7 , further comprising at least one of:
forming the array of two-terminal switching devices among a single array of conductive lines of the memory device; or
forming the array of two-terminal switching devices among multiple stacked conductive lines of the memory device.
10. A memory device, comprising:
a substrate comprising an array of transistors;
an array of two-terminal memory devices overlying the array of transistors, wherein respective two-terminal memory devices are connected electrically in parallel with respective transistors to form respective one resistor-one transistor memory devices, the array of transistors and the array of two-terminal memory devices forming a memory device array comprising the one resistor-one transistor memory devices;
a first select transistor configured to connect or disconnect a first end of the memory device array to a sourceline; and
a second select transistor configured to connect or disconnect a second end of the memory device array to a bitline, wherein respective one resistor-one transistor memory devices of the memory device array are each about 4F 2 in area.
11. The memory device of claim 10 , wherein the array of two-terminal memory devices includes a two-terminal memory cell comprising a bottom electrode, a switching layer and a top electrode.
12. The memory device of claim 11 , wherein the bottom electrode, switching layer and top electrode are layered in a direction approximately normal to a top surface of the substrate.
13. The memory device of claim 12 , wherein the two-terminal memory cell is formed between a pair of back-end-of-line (BEOL) metal layers of the memory device, and wherein a second two-terminal memory cell of the array of two-terminal memory devices is formed between a second pair of BEOL metal layers of the memory device.
14. The memory device of claim 13 , wherein at least two of the array of two-terminal memory devices are formed between the pair of BEOL metal layers.
15. The memory device of claim 14 , wherein at least two additional of the array of two-terminal memory devices are formed between the second pair of BEOL metal layers.
16. The memory device of claim 11 , wherein the bottom electrode, switching layer and top electrode are layered in a direction approximately parallel to a top surface of the substrate.
17. The memory device of claim 16 , wherein the bottom electrode, switching layer and top electrode are thin films that combine to a thickness equal to about 1F in length.
18. The memory device of claim 16 , further comprising a set of conductive lines respectively connected to source or drain contacts of the array of transistors.
19. The memory device of claim 18 , wherein the bottom electrode, switching layer and top electrode of the two-terminal memory cell are positioned between a first of the set of conductive lines and a second of the set of conductive lines.
20. The memory device of claim 18 , wherein the bottom electrode, switching layer and top electrode of the two-terminal memory cell are offset in position with respect to vertical edges of the set of conductive lines.