Memory utilization analysis for memory management systems
Memory management systems and methods are provided in which n-bit translation counters are included within page table entry (PTE) data structures to count of number of times that translations are performed using the PTEs of pages. For example, a method for managing memory includes: receiving a virtual address from an executing process, wherein the virtual address references a virtual page frame number (VPFN) in a virtual address space associated with the executing process; accessing a PTE for translating the VPFN to a page frame number (PFN) in physical memory; incrementing a n-bit translation counter within the accessed PTE in response to the translating; and accessing a memory location within the PFN in the physical memory, which corresponds to the virtual address.
1. A method for managing memory, comprising:
receiving a virtual address from an executing process, wherein the virtual address references a virtual page frame number (VPFN) in a virtual address space associated with the executing process;
accessing a page table entry (PTE) for translating the VPFN to a page frame number (PFN) of a memory page in a physical memory;
incrementing a count value of a n-bit translation counter within the accessed PTE in response to the translating, wherein the count value of the n-bit translation counter indicates a number of times that said PTE has been accessed to translate the VPFN to the PFN of the memory page in the physical memory;
accessing a memory location within the PFN of the memory page in the physical memory, which corresponds to the virtual address;
tracking a number of resets of the n-bit translation counter within said PTE as a result of overflow conditions of the n-bit translation counter during a given period of time;
determining a current count value of the n-bit translation counter within said PTE for the given period of time;
determining a frequency at which the executing process is accessing the memory page associated with the VPFN during the given period of time based on the current count value of the n-bit translation counter within said PTE and the tracked number of resets of the n-bit translation counter within said PTE, wherein the frequency comprises a rate at which the memory page is accessed during the given period of time; and
utilizing the determined frequency to track memory usage of the memory page associated with the VPFN.
2. The method of claim 1 , wherein the n-bit translation counter is implemented using reserved bits within a data structure of the PTE.
3. The method of claim 1 , wherein accessing the PTE comprises accessing the PTE in a translation lookaside buffer (TLB), and wherein the n-bit translation counter is incremented within the PTE in the TLB.
4. The method of claim 3 , wherein accessing the PTE in the TLB and incrementing the n-bit translation counter within the accessed PTE is performed by a hardware memory management unit.
5. The method of claim 3 , further comprising:
disabling the n-bit translation counter within the PTE in the TLB when the n-bit translation counter overflows; and
enabling the n-bit translation counter within the PTE, when an operating system or hypervisor resets the n-bit translation counter within a corresponding PTE in a page table.
6. The method of claim 1 , further comprising utilizing a count value of the n-bit translation counter within the PTE as part of a TLB replacement policy to determine if the PTE is a candidate for eviction from the TLB.
7. The method of claim 1 , further comprising utilizing a count value of the n-bit translation counter within the PTE as part of a page replacement policy to determine if a page which corresponds to the PTE is a candidate to be paged-out from the physical memory.
8. The method of claim 1 , further comprising utilizing the tracked memory usage for the memory page associated with the VPFN to determine which level of memory in a tiered memory framework comprising multiple tier levels of physical memory, to store the memory page.
9. An article of manufacture comprising a processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code is executable by a processor to perform method steps comprising:
receiving a virtual address from an executing process, wherein the virtual address references a virtual page frame number (VPFN) in a virtual address space associated with the executing process;
accessing a page table entry (PTE) for translating the VPFN to a page frame number (PFN) of a memory page in a physical memory;
incrementing a count value of a n-bit translation counter within the accessed PTE in response to the translating, wherein the count value of the n-bit translation counter indicates a number of times that said PTE has been accessed to translate the VPFN to the PFN of the memory page in the physical memory;
accessing a memory location within the PFN of the memory page in the physical memory, which corresponds to the virtual address;
tracking a number of resets of the n-bit translation counter within said PTE as a result of overflow conditions of the n-bit translation counter during a given period of time;
determining a current count value of the n-bit translation counter within said PTE for the given period of time;
determining a frequency at which the executing process is accessing the memory page associated with the VPFN during the given period of time based on the current count value of the n-bit translation counter within said PTE and the tracked number of resets of the n-bit translation counter within said PTE, wherein the frequency comprises a rate at which the memory page is accessed during the given period of time; and
utilizing the determined frequency to track memory usage of the memory page associated with the VPFN.
10. The article of manufacture of claim 9 , wherein the n-bit translation counter is implemented using reserved bits within a data structure of the PTE.
11. The article of manufacture of claim 9 , wherein accessing the PTE comprises accessing the PTE in a translation lookaside buffer (TLB), and wherein the n-bit translation counter is incremented within the PTE in the TLB.
12. The article of manufacture of claim 11 , wherein the program code is executable by the processor to perform method steps comprising:
disabling the n-bit translation counter within the PTE in the TLB when the n-bit translation counter overflows; and
enabling the n-bit translation counter within the PTE, when an operating system or hypervisor resets the n-bit translation counter within a corresponding PTE in a page table.
13. The article of manufacture of claim 9 , wherein the program code is executable by the processor to perform a process which comprises utilizing a count value of the n-bit translation counter within the PTE as part of a TLB replacement policy to determine if the PTE is a candidate for eviction from the TLB.
14. The article of manufacture of claim 9 , wherein the program code is executable by the processor to perform a process which comprises utilizing a count value of the n-bit translation counter within the PTE as part of a page replacement policy to determine if a page which corresponds to the PTE is a candidate to be paged-out from the physical memory.
15. The article of manufacture of claim 9 , wherein the program code is executable by the processor to perform a process which comprises utilizing the tracked memory usage for the memory page associated with the VPFN to determine which level of memory in a tiered memory framework comprising multiple tier levels of physical memory, to store the memory page.
16. An apparatus, comprising:
a processor; and
a physical memory to store program instructions that are executed by the processor to perform a method comprising:
receiving a virtual address from an executing process, wherein the virtual address references a virtual page frame number (VPFN) in a virtual address space associated with the executing process;
accessing a page table entry (PTE) for translating the VPFN to a page frame number (PFN) of a memory page in a physical memory;
incrementing a count value of a n-bit translation counter within the accessed PTE in response to the translating, wherein the count value of the n-bit translation counter indicates a number of times that said PTE has been accessed to translate the VPFN to the PFN of the memory page in the physical memory;
accessing a memory location within the PFN of the memory page in the physical memory, which corresponds to the virtual address;
tracking a number of resets of the n-bit translation counter within said PTE as a result of overflow conditions of the n-bit translation counter during a given period of time;
determining a current count value of the n-bit translation counter within said PTE for the given period of time;
determining a frequency at which the executing process is accessing the memory page associated with the VPFN during the given period of time based on the current count value of the n-bit translation counter within said PTE and the tracked number of resets of the n-bit translation counter within said PTE, wherein the frequency comprises a rate at which the memory page is accessed during the given period of time; and
utilizing the determined frequency to track memory usage of the memory page associated with the VPFN.
17. The apparatus of claim 16 , wherein the n-bit translation counter is implemented using reserved bits within a data structure of the PTE.
18. The apparatus of claim 16 , wherein the PTE is accessed in a translation lookaside buffer (TLB), and wherein the n-bit translation counter is incremented within the PTE in the TLB.
19. The apparatus of claim 18 , wherein the n-bit translation counter within the PTE in the TLB is disabled when the n-bit translation counter overflows, and wherein the n-bit translation counter within the PTE is enabled when an operating system or hypervisor resets the n-bit translation counter within a corresponding PTE in a page table.
20. The apparatus of claim 16 , wherein a count value of the n-bit translation counter within the PTE it utilized (i) as part of a TLB replacement policy to determine if the PTE is a candidate for eviction from the TLB and (ii) as part of a page replacement policy to determine if a page which corresponds to the PTE is a candidate to be paged-out from the physical memory.